^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for STMicroelectronics STM32 I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This I2C controller is described in the STM32F429/439 Soc reference manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Please see below a link to the documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * http://www.st.com/resource/en/reference_manual/DM00031020.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) M'boumba Cedric Madianga 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This driver is based on i2c-st.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "i2c-stm32.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* STM32F4 I2C offset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STM32F4_I2C_CR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STM32F4_I2C_CR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STM32F4_I2C_DR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STM32F4_I2C_SR1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STM32F4_I2C_SR2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STM32F4_I2C_CCR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STM32F4_I2C_TRISE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32F4_I2C_FLTR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* STM32F4 I2C control 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32F4_I2C_CR1_POS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32F4_I2C_CR1_ACK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32F4_I2C_CR1_STOP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STM32F4_I2C_CR1_START BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32F4_I2C_CR1_PE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* STM32F4 I2C control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STM32F4_I2C_CR2_FREQ_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STM32F4_I2C_CR2_FREQ(n) ((n) & STM32F4_I2C_CR2_FREQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32F4_I2C_CR2_ITBUFEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32F4_I2C_CR2_ITEVTEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32F4_I2C_CR2_ITERREN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32F4_I2C_CR2_IRQ_MASK (STM32F4_I2C_CR2_ITBUFEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) STM32F4_I2C_CR2_ITEVTEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) STM32F4_I2C_CR2_ITERREN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* STM32F4 I2C Status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32F4_I2C_SR1_AF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32F4_I2C_SR1_ARLO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32F4_I2C_SR1_BERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32F4_I2C_SR1_TXE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32F4_I2C_SR1_RXNE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32F4_I2C_SR1_BTF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32F4_I2C_SR1_ADDR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32F4_I2C_SR1_SB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32F4_I2C_SR1_ITEVTEN_MASK (STM32F4_I2C_SR1_BTF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) STM32F4_I2C_SR1_ADDR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) STM32F4_I2C_SR1_SB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STM32F4_I2C_SR1_ITBUFEN_MASK (STM32F4_I2C_SR1_TXE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) STM32F4_I2C_SR1_RXNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STM32F4_I2C_SR1_ITERREN_MASK (STM32F4_I2C_SR1_AF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) STM32F4_I2C_SR1_ARLO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) STM32F4_I2C_SR1_BERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* STM32F4 I2C Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STM32F4_I2C_SR2_BUSY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* STM32F4 I2C Control Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STM32F4_I2C_CCR_CCR_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STM32F4_I2C_CCR_CCR(n) ((n) & STM32F4_I2C_CCR_CCR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32F4_I2C_CCR_FS BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STM32F4_I2C_CCR_DUTY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* STM32F4 I2C Trise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STM32F4_I2C_TRISE_VALUE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STM32F4_I2C_TRISE_VALUE(n) ((n) & STM32F4_I2C_TRISE_VALUE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STM32F4_I2C_MIN_STANDARD_FREQ 2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STM32F4_I2C_MIN_FAST_FREQ 6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32F4_I2C_MAX_FREQ 46U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HZ_TO_MHZ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct stm32f4_i2c_msg - client specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @addr: 8-bit slave addr, including r/w bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @count: number of bytes to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @result: result of the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @stop: last I2C msg to be sent, i.e. STOP to be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct stm32f4_i2c_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * struct stm32f4_i2c_dev - private data of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @adap: I2C adapter for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @dev: device for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @base: virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @complete: completion of I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @clk: hw i2c clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @speed: I2C clock frequency of the controller. Standard or Fast are supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @parent_rate: I2C clock parent rate in MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @msg: I2C transfer information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct stm32f4_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct stm32f4_i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel_relaxed(readl_relaxed(reg) | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel_relaxed(readl_relaxed(reg) & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 cr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * To reach 100 kHz, the parent clk frequency should be between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * a minimum value of 2 MHz and a maximum value of 46 MHz due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * to hardware limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (freq < STM32F4_I2C_MIN_STANDARD_FREQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) freq > STM32F4_I2C_MAX_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "bad parent clk freq for standard mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * To be as close as possible to 400 kHz, the parent clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * frequency should be between a minimum value of 6 MHz and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * maximum value of 46 MHz due to hardware limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (freq < STM32F4_I2C_MIN_FAST_FREQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) freq > STM32F4_I2C_MAX_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "bad parent clk freq for fast mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cr2 |= STM32F4_I2C_CR2_FREQ(freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 trise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * These bits must be programmed with the maximum SCL rise time given in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * the I2C bus specification, incremented by 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * In standard mode, the maximum allowed SCL rise time is 1000 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * programmed with 0x9. (1000 ns / 125 ns + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * So, for I2C standard mode TRISE = FREQ[5:0] + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * In fast mode, the maximum allowed SCL rise time is 300 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * programmed with 0x3. (300 ns / 125 ns + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * is not higher than 46 MHz . As a result trise is at most 4 bits wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * and so fits into the TRISE bits [5:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) trise = freq + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) trise = freq * 3 / 10 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) i2c_dev->base + STM32F4_I2C_TRISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 ccr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * In standard mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * t_scl_high = t_scl_low = CCR * I2C parent clk period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * So to reach 100 kHz, we have:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * CCR = I2C parent rate / (100 kHz * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * For example with parent rate = 2 MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * CCR = 2000000 / (100000 * 2) = 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Function stm32f4_i2c_set_periph_clk_freq made sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * parent rate is not higher than 46 MHz . As a result val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * is at most 8 bits wide and so fits into the CCR bits [11:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * In fast mode, we compute CCR with duty = 0 as with low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * frequencies we are not able to reach 400 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * In that case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * t_scl_high = CCR * I2C parent clk period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * t_scl_low = 2 * CCR * I2C parent clk period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * So, CCR = I2C parent rate / (400 kHz * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * For example with parent rate = 6 MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * CCR = 6000000 / (400000 * 3) = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Function stm32f4_i2c_set_periph_clk_freq made sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * parent rate is not higher than 46 MHz . As a result val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * is at most 6 bits wide and so fits into the CCR bits [11:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Select Fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ccr |= STM32F4_I2C_CCR_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ccr |= STM32F4_I2C_CCR_CCR(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * stm32f4_i2c_hw_config() - Prepare I2C block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) stm32f4_i2c_set_rise_time(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) stm32f4_i2c_set_speed_mode(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) !(status & STM32F4_I2C_SR2_BUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_dbg(i2c_dev->dev, "bus not free\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * stm32f4_i2c_write_ byte() - Write a byte in the data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @byte: Data to write in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * stm32f4_i2c_write_msg() - Fill the data register in write mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * This function fills the data register with I2C transfer buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) stm32f4_i2c_write_byte(i2c_dev, *msg->buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) msg->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *msg->buf++ = rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) msg->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) stm32f4_i2c_disable_irq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg = i2c_dev->base + STM32F4_I2C_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (msg->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) stm32f4_i2c_write_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * Disable buffer interrupts for RX not empty and TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * empty events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) stm32f4_i2c_terminate_xfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * This function is called when a new data is received in data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) switch (msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) stm32f4_i2c_disable_irq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) stm32f4_i2c_read_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * for N-byte reception with N > 3, we do not have to read the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * register when RX not empty event occurs as we have to wait for byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * transferred finished event before reading data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * So, here we just disable buffer interrupt in order to avoid another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * system preemption due to RX not empty event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * For N byte reception with N > 3 we directly read data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * until N-2 data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) stm32f4_i2c_read_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * in case of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * This function is called when a new data is received in the shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * but data register has not been read yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * In order to correctly send the Stop or Repeated Start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * condition on the I2C bus, the STOP/START bit has to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * before reading the last two bytes (data N-1 and N).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * After that, we could read the last two bytes, disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * remaining interrupts and notify the end of xfer to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) reg = i2c_dev->base + STM32F4_I2C_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (msg->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) for (i = 2; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) stm32f4_i2c_read_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg = i2c_dev->base + STM32F4_I2C_CR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) stm32f4_i2c_clr_bits(reg, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * In order to correctly generate the NACK pulse after the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * received data byte, we have to enable NACK before reading N-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) reg = i2c_dev->base + STM32F4_I2C_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) stm32f4_i2c_read_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) stm32f4_i2c_read_msg(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * master receiver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) switch (msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) stm32f4_i2c_terminate_xfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Clear ADDR flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Single byte reception:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Enable NACK and reset POS (Acknowledge position).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Then, clear ADDR flag and set STOP or RepSTART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * In that way, the NACK and STOP or RepStart pulses will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * sent as soon as the byte will be received in shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (msg->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cr1 |= STM32F4_I2C_CR1_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cr1 |= STM32F4_I2C_CR1_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * 2-byte reception:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Enable NACK, set POS (NACK position) and clear ADDR flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * In that way, NACK will be sent for the next byte which will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * be received in the shift register instead of the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cr1 &= ~STM32F4_I2C_CR1_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) cr1 |= STM32F4_I2C_CR1_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * N-byte reception:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Enable ACK, reset POS (ACK postion) and clear ADDR flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * In that way, ACK will be sent as soon as the current byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * will be received in the shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cr1 |= STM32F4_I2C_CR1_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) cr1 &= ~STM32F4_I2C_CR1_POS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @data: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct stm32f4_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 status, ien, event, cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Update possible_status if buffer interrupt is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ien & STM32F4_I2C_CR2_ITBUFEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) event = status & possible_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "spurious evt irq (status=0x%08x, ien=0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) status, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Start condition generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (event & STM32F4_I2C_SR1_SB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stm32f4_i2c_write_byte(i2c_dev, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* I2C Address sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (event & STM32F4_I2C_SR1_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (msg->addr & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) stm32f4_i2c_handle_rx_addr(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Enable buffer interrupts for RX not empty and TX empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cr2 |= STM32F4_I2C_CR2_ITBUFEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* TX empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) stm32f4_i2c_handle_write(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* RX not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) stm32f4_i2c_handle_read(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * The BTF (Byte Transfer finished) event occurs when:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * - in reception : a new byte is received in the shift register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * but the previous byte has not been read yet from data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * - in transmission: a new byte should be sent but the data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * has not been written yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (event & STM32F4_I2C_SR1_BTF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (msg->addr & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) stm32f4_i2c_handle_rx_done(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) stm32f4_i2c_handle_write(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @data: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct stm32f4_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (status & STM32F4_I2C_SR1_ARLO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) status &= ~STM32F4_I2C_SR1_ARLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) msg->result = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Acknowledge failure:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * In master transmitter mode a Stop must be generated by software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (status & STM32F4_I2C_SR1_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!(msg->addr & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) reg = i2c_dev->base + STM32F4_I2C_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) status &= ~STM32F4_I2C_SR1_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msg->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (status & STM32F4_I2C_SR1_BERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) status &= ~STM32F4_I2C_SR1_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) msg->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) stm32f4_i2c_disable_irq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * stm32f4_i2c_xfer_msg() - Transfer a single I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @msg: I2C message to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * @is_first: first message of the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @is_last: last message of the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct i2c_msg *msg, bool is_first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bool is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) f4_msg->addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) f4_msg->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) f4_msg->count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) f4_msg->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) f4_msg->stop = is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Enable events and errors interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (is_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = stm32f4_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* START generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) timeout = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i2c_dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = f4_msg->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * stm32f4_i2c_xfer() - Transfer combined I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * @i2c_adap: Adapter pointer to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * @msgs: Pointer to data to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * @num: Number of messages to be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = clk_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(i2c_dev->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) for (i = 0; i < num && !ret; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_disable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return (ret < 0) ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static u32 stm32f4_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct i2c_algorithm stm32f4_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .master_xfer = stm32f4_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .functionality = stm32f4_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int stm32f4_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct stm32f4_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 irq_event, irq_error, clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) irq_event = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (!irq_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(&pdev->dev, "IRQ event missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) irq_error = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!irq_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(&pdev->dev, "IRQ error missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (IS_ERR(i2c_dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_err(&pdev->dev, "Error: Missing controller clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return PTR_ERR(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "Error: Missing reset ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) i2c_dev->speed = STM32_I2C_SPEED_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(&pdev->dev, "Failed to request irq event %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) irq_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(&pdev->dev, "Failed to request irq error %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) irq_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = stm32f4_i2c_hw_config(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) adap = &i2c_dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) i2c_set_adapdata(adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) adap->timeout = 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) adap->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) adap->algo = &stm32f4_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) init_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_disable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) clk_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int stm32f4_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) i2c_del_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) clk_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const struct of_device_id stm32f4_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) { .compatible = "st,stm32f4-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MODULE_DEVICE_TABLE(of, stm32f4_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static struct platform_driver stm32f4_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .name = "stm32f4-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .of_match_table = stm32f4_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .probe = stm32f4_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .remove = stm32f4_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) module_platform_driver(stm32f4_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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