^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * I2C master mode controller driver, used in STMicroelectronics devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Maxime Coquelin <maxime.coquelin@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* SSC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SSC_BRG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SSC_TBUF 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SSC_RBUF 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SSC_CTL 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSC_IEN 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SSC_STA 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSC_I2C 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SSC_SLAD 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSC_REP_START_HOLD 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSC_START_HOLD 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SSC_REP_START_SETUP 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SSC_DATA_SETUP 0x02C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SSC_STOP_SETUP 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SSC_BUS_FREE 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SSC_TX_FSTAT 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SSC_RX_FSTAT 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SSC_PRE_SCALER_BRG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SSC_CLR 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SSC_NOISE_SUPP_WIDTH 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SSC_PRSCALER 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SSC_PRSCALER_DATAOUT 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SSC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SSC_CTL_DATA_WIDTH_9 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SSC_CTL_DATA_WIDTH_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SSC_CTL_BM 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSC_CTL_HB BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SSC_CTL_PH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SSC_CTL_PO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSC_CTL_SR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SSC_CTL_MS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SSC_CTL_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SSC_CTL_LPB BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SSC_CTL_EN_TX_FIFO BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SSC_CTL_EN_RX_FIFO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SSC_CTL_EN_CLST_RX BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* SSC Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SSC_IEN_RIEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SSC_IEN_TIEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SSC_IEN_TEEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SSC_IEN_REEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SSC_IEN_PEEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SSC_IEN_AASEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SSC_IEN_STOPEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SSC_IEN_ARBLEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SSC_IEN_NACKEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SSC_IEN_REPSTRTEN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SSC_IEN_TX_FIFO_HALF BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* SSC Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SSC_STA_RIR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SSC_STA_TIR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SSC_STA_TE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SSC_STA_RE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SSC_STA_PE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SSC_STA_CLST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SSC_STA_AAS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SSC_STA_STOP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SSC_STA_ARBL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SSC_STA_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SSC_STA_NACK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SSC_STA_REPSTRT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SSC_STA_TX_FIFO_HALF BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SSC_STA_TX_FIFO_FULL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SSC_STA_RX_FIFO_HALF BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* SSC I2C Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SSC_I2C_I2CM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SSC_I2C_STRTG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SSC_I2C_STOPG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SSC_I2C_ACKG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SSC_I2C_AD10 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SSC_I2C_TXENB BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SSC_I2C_REPSTRTG BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SSC_I2C_SLAVE_DISABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* SSC Tx FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SSC_TX_FSTAT_STATUS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* SSC Rx FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SSC_RX_FSTAT_STATUS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* SSC Clear bit operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SSC_CLR_SSCAAS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SSC_CLR_SSCSTOP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SSC_CLR_SSCARBL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SSC_CLR_NACK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SSC_CLR_REPSTRT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* SSC Clock Prescaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SSC_PRSC_VALUE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SSC_TXFIFO_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SSC_RXFIFO_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum st_i2c_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) I2C_MODE_STANDARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) I2C_MODE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) I2C_MODE_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * struct st_i2c_timings - per-Mode tuning parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @rate: I2C bus rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @rep_start_hold: I2C repeated start hold time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @rep_start_setup: I2C repeated start set up time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @start_hold: I2C start hold time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @data_setup_time: I2C data set up time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @stop_setup_time: I2C stop set up time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @bus_free_time: I2C bus free time requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @sda_pulse_min_limit: I2C SDA pulse mini width limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct st_i2c_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 rep_start_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 rep_start_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 start_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 data_setup_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 stop_setup_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 bus_free_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 sda_pulse_min_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * struct st_i2c_client - client specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @addr: 8-bit slave addr, including r/w bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @count: number of bytes to be transfered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @xfered: number of bytes already transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @result: result of the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @stop: last I2C msg to be sent, i.e. STOP to be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct st_i2c_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * struct st_i2c_dev - private data of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @adap: I2C adapter for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @dev: device for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @base: virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @complete: completion of I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @irq: interrupt line for th controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @clk: hw ssc block clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @mode: I2C mode of the controller. Standard or Fast only supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @scl_min_width_us: SCL line minimum pulse width in us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @sda_min_width_us: SDA line minimum pulse width in us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @client: I2C transfert information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @busy: I2C transfer on-going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct st_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 scl_min_width_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 sda_min_width_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct st_i2c_client client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(readl_relaxed(reg) | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel_relaxed(readl_relaxed(reg) & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * From I2C Specifications v0.5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * All the values below have +10% margin added to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * compatible with some out-of-spec devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * like HDMI link of the Toshiba 19AV600 TV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct st_i2c_timings i2c_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [I2C_MODE_STANDARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .rate = I2C_MAX_STANDARD_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .rep_start_hold = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .rep_start_setup = 5170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .start_hold = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .data_setup_time = 275,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .stop_setup_time = 4400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .bus_free_time = 5170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [I2C_MODE_FAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .rate = I2C_MAX_FAST_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .rep_start_hold = 660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .rep_start_setup = 660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .start_hold = 660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .data_setup_time = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .stop_setup_time = 660,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .bus_free_time = 1430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int count, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Counter only counts up to 7 but fifo size is 8...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * When fifo is full, counter is 0 and RIR bit of status register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) count = SSC_RXFIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SSC_RX_FSTAT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) readl_relaxed(i2c_dev->base + SSC_RBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * FIFO needs to be emptied before reseting the IP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * else the controller raises a BUSY error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) st_i2c_flush_rx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 val, ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) st_i2c_soft_reset(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel_relaxed(val, i2c_dev->base + SSC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* SSC Control register setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel_relaxed(val, i2c_dev->base + SSC_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rate = clk_get_rate(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ns_per_clk = 1000000000 / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Baudrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) val = rate / (2 * t->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel_relaxed(val, i2c_dev->base + SSC_BRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Pre-scaler baudrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Enable I2C mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Repeated start hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val = t->rep_start_hold / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Repeated start set up time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = t->rep_start_setup / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Start hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val = t->start_hold / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Data set up time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = t->data_setup_time / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Stop set up time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val = t->stop_setup_time / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Bus free time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val = t->bus_free_time / ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Prescalers set up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = rate / 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Noise suppression witdh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val = i2c_dev->scl_min_width_us * rate / 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Noise suppression max output data delay width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) val = i2c_dev->sda_min_width_us * rate / 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(i2c_dev->dev, "Trying to recover bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * SSP IP is dual role SPI/I2C to generate 9 clock pulses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * we switch to SPI node, 9 bit words and write a 0. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * has been validate with a oscilloscope and is easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * than switching to GPIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writel_relaxed(0, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) st_i2c_hw_config(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) usleep_range(8000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) writel_relaxed(0, i2c_dev->base + SSC_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 0; i < 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) sta = readl_relaxed(i2c_dev->base + SSC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!(sta & SSC_STA_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = i2c_recover_bus(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @byte: Data to write in the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 tbuf = byte << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * This functions fills the Tx FIFO with I2C transfert buffer when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 tx_fstat, sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sta = readl_relaxed(i2c_dev->base + SSC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (sta & SSC_STA_TX_FIFO_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) tx_fstat &= SSC_TX_FSTAT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (c->count < (SSC_TXFIFO_SIZE - tx_fstat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) i = c->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i = SSC_TXFIFO_SIZE - tx_fstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) for (; i > 0; i--, c->count--, c->buf++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) st_i2c_write_tx_fifo(i2c_dev, *c->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @max: Maximum amount of data to fill into the Tx FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * This functions fills the Tx FIFO with fixed pattern when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * in read mode to trigger clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 tx_fstat, sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) sta = readl_relaxed(i2c_dev->base + SSC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (sta & SSC_STA_TX_FIFO_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tx_fstat &= SSC_TX_FSTAT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (max < (SSC_TXFIFO_SIZE - tx_fstat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) i = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i = SSC_TXFIFO_SIZE - tx_fstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) for (; i > 0; i--, c->xfered++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) st_i2c_write_tx_fifo(i2c_dev, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 i, sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sta = readl_relaxed(i2c_dev->base + SSC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (sta & SSC_STA_RIR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) i = SSC_RXFIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i &= SSC_RX_FSTAT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) for (; (i > 0) && (c->count > 0); i--, c->count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *c->buf++ = (u8)rbuf & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) st_i2c_flush_rx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (c->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) st_i2c_flush_rx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!c->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* End of xfer, send stop or repstart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) st_i2c_terminate_xfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) st_i2c_wr_fill_tx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Trash the address read back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!c->xfered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) readl_relaxed(i2c_dev->base + SSC_RBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) st_i2c_read_rx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!c->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* End of xfer, send stop or repstart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) st_i2c_terminate_xfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } else if (c->count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Penultimate byte to xfer, disable ACK gen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Last received byte is to be handled by NACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel_relaxed(ien, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * st_i2c_isr() - Interrupt routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @data: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static irqreturn_t st_i2c_isr_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct st_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 sta, ien;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ien = readl_relaxed(i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) sta = readl_relaxed(i2c_dev->base + SSC_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Use __fls() to check error bits first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) it = __fls(sta & ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (it < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sta, ien);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) switch (1 << it) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case SSC_STA_TE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (c->addr & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) st_i2c_handle_read(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) st_i2c_handle_write(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case SSC_STA_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case SSC_STA_REPSTRT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) writel_relaxed(0, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case SSC_STA_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Last received byte handled by NACK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) st_i2c_handle_read(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) writel_relaxed(it, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) c->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case SSC_STA_ARBL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) writel_relaxed(it, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) c->result = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "it %d unhandled (sta=0x%04x)\n", it, sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Read IEN register to ensure interrupt mask write is effective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * before re-enabling interrupt at GIC level, and thus avoid spurious
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) readl(i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * st_i2c_xfer_msg() - Transfer a single I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * @i2c_dev: Controller's private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @msg: I2C message to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @is_first: first message of the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @is_last: last message of the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bool is_first, bool is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct st_i2c_client *c = &i2c_dev->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 ctl, i2c, it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) c->addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) c->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) c->count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) c->xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) c->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) c->stop = is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) i2c = SSC_I2C_TXENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (c->addr & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c |= SSC_I2C_ACKG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Write slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) st_i2c_write_tx_fifo(i2c_dev, c->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Pre-fill Tx fifo with data in case of write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!(c->addr & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) st_i2c_wr_fill_tx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel_relaxed(it, i2c_dev->base + SSC_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (is_first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = st_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) timeout = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) i2c_dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = c->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) c->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) i2c_dev->base + SSC_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * st_i2c_xfer() - Transfer a single I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @i2c_adap: Adapter pointer to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @msgs: Pointer to data to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * @num: Number of messages to be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) i2c_dev->busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pinctrl_pm_select_default_state(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) st_i2c_hw_config(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) for (i = 0; (i < num) && !ret; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pinctrl_pm_select_idle_state(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) i2c_dev->busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return (ret < 0) ? ret : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int st_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (i2c_dev->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int st_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Go in idle state if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define ST_I2C_PM (&st_i2c_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define ST_I2C_PM NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static u32 st_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const struct i2c_algorithm st_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .master_xfer = st_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .functionality = st_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static struct i2c_bus_recovery_info st_i2c_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .recover_bus = st_i2c_recover_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int st_i2c_of_get_deglitch(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct st_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) &i2c_dev->scl_min_width_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &i2c_dev->sda_min_width_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int st_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct st_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) i2c_dev->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!i2c_dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&pdev->dev, "IRQ missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i2c_dev->clk = of_clk_get_by_name(np, "ssc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (IS_ERR(i2c_dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_err(&pdev->dev, "Unable to request clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return PTR_ERR(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) i2c_dev->mode = I2C_MODE_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (!ret && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) i2c_dev->mode = I2C_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) NULL, st_i2c_isr_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) IRQF_ONESHOT, pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pinctrl_pm_select_default_state(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* In case idle state available, select it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pinctrl_pm_select_idle_state(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = st_i2c_of_get_deglitch(np, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) adap = &i2c_dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) i2c_set_adapdata(adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) adap->timeout = 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) adap->retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) adap->algo = &st_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) adap->bus_recovery_info = &st_i2c_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) init_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int st_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) i2c_del_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const struct of_device_id st_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) { .compatible = "st,comms-ssc-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) { .compatible = "st,comms-ssc4-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MODULE_DEVICE_TABLE(of, st_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct platform_driver st_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "st-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .of_match_table = st_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .pm = ST_I2C_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .probe = st_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .remove = st_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) module_platform_driver(st_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_DESCRIPTION("STMicroelectronics I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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