^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2C_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2C_ADDR_CFG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_COUNT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2C_RX 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2C_TX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_HSMODE_CFG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_VERSION 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADDR_DVD0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADDR_DVD1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADDR_STA0_DVD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADDR_RST 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* I2C_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STP_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FIFO_AF_LVL_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FIFO_AF_LVL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FIFO_AE_LVL_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FIFO_AE_LVL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_DMA_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FULL_INTEN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EMPTY_INTEN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_DVD_OPT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_OUT_OPT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_TRIM_OPT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_HS_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_MODE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_INT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* I2C_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDA_IN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCL_IN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FIFO_FULL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FIFO_EMPTY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_RX_ACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* ADDR_RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_FIFO_DEEP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_FIFO_FULL_THLD 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_FIFO_EMPTY_THLD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2C_DATA_STEP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2C_ADDR_DVD0_CALC(high, low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_ADDR_DVD1_CALC(high, low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* timeout (ms) for pm runtime autosuspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPRD_I2C_PM_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* timeout (ms) for transfer message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_XFER_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SPRD i2c data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct sprd_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 bus_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(count, i2c_dev->base + I2C_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 tmp = readl(i2c_dev->base + I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 tmp = readl(i2c_dev->base + I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(I2C_RST, i2c_dev->base + ADDR_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writeb(buf[i], i2c_dev->base + I2C_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) buf[i] = readb(i2c_dev->base + I2C_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tmp &= ~FIFO_AF_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp |= full_thld << FIFO_AF_LVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) writel(tmp, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp &= ~FIFO_AE_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) tmp |= empty_thld << FIFO_AE_LVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(tmp, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tmp |= FULL_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tmp &= ~FULL_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(tmp, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tmp |= EMPTY_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tmp &= ~EMPTY_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(tmp, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 i2c_count = i2c_dev->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct i2c_msg *msg = i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) i2c_dev->count -= I2C_FIFO_FULL_THLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) i2c_dev->buf += I2C_FIFO_FULL_THLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * If the read data count is larger than rx fifo full threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * we should enable the rx fifo full interrupt to read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sprd_i2c_set_fifo_full_int(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) i2c_dev->buf += need_tran;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) i2c_dev->count -= need_tran;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * If the write data count is arger than tx fifo depth which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * means we can not write all data in one time, then we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * enable the tx fifo empty interrupt to write again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (i2c_count > I2C_FIFO_DEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct i2c_msg *msg, bool is_last_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i2c_dev->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) i2c_dev->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) i2c_dev->count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sprd_i2c_reset_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sprd_i2c_set_devaddr(i2c_dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sprd_i2c_set_count(i2c_dev, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sprd_i2c_opt_mode(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sprd_i2c_send_stop(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sprd_i2c_opt_mode(i2c_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * We should enable rx fifo full interrupt to get data when receiving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * full data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sprd_i2c_set_fifo_full_int(i2c_dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sprd_i2c_data_transfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sprd_i2c_opt_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) time_left = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msecs_to_jiffies(I2C_XFER_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return i2c_dev->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int im, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (im = 0; im < num - 1; im++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) goto err_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err_msg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pm_runtime_mark_last_busy(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) pm_runtime_put_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret < 0 ? ret : im;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u32 sprd_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct i2c_algorithm sprd_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .master_xfer = sprd_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .functionality = sprd_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 apb_clk = i2c_dev->src_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * From I2C databook, the prescale calculation formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * prescale = freq_i2c / (4 * freq_scl) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 i2c_dvd = apb_clk / (4 * freq) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * From I2C databook, the high period of SCL clock is recommended as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * 40% (2/5), and the low period of SCL clock is recommended as 60%
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * (3/5), then the formula should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * high = (prescale * 2 * 2) / 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * low = (prescale * 2 * 3) / 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 high = ((i2c_dvd << 1) * 2) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 low = ((i2c_dvd << 1) * 3) / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(div0, i2c_dev->base + ADDR_DVD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) writel(div1, i2c_dev->base + ADDR_DVD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Start hold timing = hold time(us) * source clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (freq == I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else if (freq == I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 tmp = I2C_DVD_OPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(tmp, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sprd_i2c_reset_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) sprd_i2c_clear_irq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) tmp = readl(i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct sprd_i2c *i2c_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct i2c_msg *msg = i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 i2c_tran;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) i2c_tran = i2c_dev->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * If we got one ACK from slave when writing data, and we did not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * finish this transmission (i2c_tran is not zero), then we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * continue to write data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * For reading data, ack is always true, if i2c_tran is not 0 which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * means we still need to contine to read data from slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (i2c_tran && ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sprd_i2c_data_transfer(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) i2c_dev->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * If we did not get one ACK from slave when writing data, we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * return -EIO to notify users.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!ack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) i2c_dev->err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) else if (msg->flags & I2C_M_RD && i2c_dev->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Transmission is done and clear ack and start operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sprd_i2c_clear_ack(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sprd_i2c_clear_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct sprd_i2c *i2c_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct i2c_msg *msg = i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 i2c_tran;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) i2c_tran = i2c_dev->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * If we did not get one ACK from slave when writing data, then we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * should finish this transmission since we got some errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * When writing data, if i2c_tran == 0 which means we have writen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * done all data, then we can finish this transmission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * When reading data, if conut < rx fifo full threshold, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * means we can read all data in one time, then we can finish this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * transmission too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!i2c_tran || !ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) sprd_i2c_clear_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sprd_i2c_clear_irq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) sprd_i2c_set_fifo_full_int(i2c_dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct clk *clk_i2c, *clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (IS_ERR(clk_i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) i2c_dev->adap.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_i2c = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk_parent = devm_clk_get(i2c_dev->dev, "source");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (IS_ERR(clk_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i2c_dev->adap.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) clk_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (clk_set_parent(clk_i2c, clk_parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) i2c_dev->src_clk = clk_get_rate(clk_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) i2c_dev->src_clk = 26000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i2c_dev->adap.nr, i2c_dev->src_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(i2c_dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(i2c_dev->dev, "i2c%d can't get the enable clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) i2c_dev->adap.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return PTR_ERR(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int sprd_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sprd_i2c *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pdev->id = of_alias_get_id(dev->of_node, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) i2c_dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (i2c_dev->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return i2c_dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) init_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "%s", "sprd-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) i2c_dev->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) i2c_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2c_dev->adap.retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) i2c_dev->adap.algo = &sprd_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) i2c_dev->adap.algo_data = i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) i2c_dev->adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) i2c_dev->adap.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) i2c_dev->adap.dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) i2c_dev->bus_freq = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* We only support 100k and 400k now, otherwise will return error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = sprd_i2c_clk_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sprd_i2c_enable(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pm_runtime_use_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pm_runtime_set_active(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pm_runtime_enable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = pm_runtime_get_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) goto err_rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = devm_request_threaded_irq(dev, i2c_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sprd_i2c_isr, sprd_i2c_isr_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) IRQF_NO_SUSPEND | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto err_rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = i2c_add_numbered_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(&pdev->dev, "add adapter failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err_rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pm_runtime_mark_last_busy(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pm_runtime_put_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) err_rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pm_runtime_put_noidle(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int sprd_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) i2c_del_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pm_runtime_put_noidle(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) i2c_mark_adapter_suspended(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) i2c_mark_adapter_resumed(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) sprd_i2c_enable(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct dev_pm_ops sprd_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sprd_i2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) sprd_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct of_device_id sprd_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { .compatible = "sprd,sc9860-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static struct platform_driver sprd_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .probe = sprd_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .remove = sprd_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .name = "sprd-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .of_match_table = sprd_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .pm = &sprd_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) module_platform_driver(sprd_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MODULE_DESCRIPTION("Spreadtrum I2C master controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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