^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This module must be considered BETA unless and until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) the chipset manufacturer releases a datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) The register definitions are based on the SiS630.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) for just about every machine for which users have reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) If this module isn't detecting your 96x south bridge, have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) look there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) We assume there can only be one SiS96x with one SMBus interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* base address register in PCI config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIS96x_BAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* SiS96x SMBus registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMB_STS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMB_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SMB_CNT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SMB_HOST_CNT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SMB_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SMB_CMD 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SMB_PCOUNT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SMB_COUNT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMB_BYTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMB_DEV_ADDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SMB_DB0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SMB_DB1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SMB_SAA 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* register count for request_region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SMB_IOSIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX_TIMEOUT 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* SiS96x SMBus constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIS96x_QUICK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIS96x_BYTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SIS96x_BYTE_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIS96x_WORD_DATA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIS96x_PROC_CALL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SIS96x_BLOCK_DATA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct pci_driver sis96x_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static struct i2c_adapter sis96x_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u16 sis96x_smbus_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline u8 sis96x_read(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return inb(sis96x_smbus_base + reg) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static inline void sis96x_write(u8 reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) outb(data, sis96x_smbus_base + reg) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Execute a SMBus transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int sis96x_transaction(int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Make sure the SMBus host is ready to start transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "Resetting...\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* kill the transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sis96x_write(SMB_HOST_CNT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* check it again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_dbg(&sis96x_adapter.dev, "Successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Turn off timeout interrupts, set fast host clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sis96x_write(SMB_CNT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* clear all (sticky) status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) temp = sis96x_read(SMB_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sis96x_write(SMB_STS, temp & 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* start the transaction by setting bit 4 and size bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* We will always wait for a fraction of a second! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) temp = sis96x_read(SMB_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (timeout > MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* device error - probably missing ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (temp & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* bus collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (temp & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Finish up by resetting the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sis96x_write(SMB_STS, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if ((temp = sis96x_read(SMB_STS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_dbg(&sis96x_adapter.dev, "Failed reset at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "end of transaction! (0x%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 command, int size, union i2c_smbus_data * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) size = SIS96x_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sis96x_write(SMB_CMD, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) size = SIS96x_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sis96x_write(SMB_CMD, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sis96x_write(SMB_BYTE, data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) size = SIS96x_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sis96x_write(SMB_CMD, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sis96x_write(SMB_BYTE, data->word & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) size = (size == I2C_SMBUS_PROC_CALL ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SIS96x_PROC_CALL : SIS96x_WORD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) status = sis96x_transaction(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if ((size != SIS96x_PROC_CALL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case SIS96x_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) case SIS96x_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data->byte = sis96x_read(SMB_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case SIS96x_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case SIS96x_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data->word = sis96x_read(SMB_BYTE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (sis96x_read(SMB_BYTE + 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static u32 sis96x_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) I2C_FUNC_SMBUS_PROC_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .smbus_xfer = sis96x_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .functionality = sis96x_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct i2c_adapter sis96x_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .algo = &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct pci_device_id sis96x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_DEVICE_TABLE (pci, sis96x_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sis96x_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u16 ww = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (sis96x_smbus_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(&dev->dev, "Only one device supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (PCI_CLASS_SERIAL_SMBUS != ww) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!sis96x_smbus_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(&dev->dev, "SiS96x SMBus base address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "not initialized!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sis96x_smbus_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) retval = acpi_check_resource_conflict(&dev->resource[SIS96x_BAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Everything is happy, let's grab the memory and set things up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!request_region(sis96x_smbus_base, SMB_IOSIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sis96x_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "already in use!\n", sis96x_smbus_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sis96x_smbus_base + SMB_IOSIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) sis96x_smbus_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* set up the sysfs linkage to our parent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sis96x_adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) snprintf(sis96x_adapter.name, sizeof(sis96x_adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((retval = i2c_add_adapter(&sis96x_adapter))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&dev->dev, "Couldn't register adapter!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) release_region(sis96x_smbus_base, SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) sis96x_smbus_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void sis96x_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (sis96x_smbus_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) i2c_del_adapter(&sis96x_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) release_region(sis96x_smbus_base, SMB_IOSIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sis96x_smbus_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct pci_driver sis96x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "sis96x_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .id_table = sis96x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .probe = sis96x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .remove = sis96x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) module_pci_driver(sis96x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("SiS96x SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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