^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * I2C bus driver for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SIRFSOC_I2C_CLK_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SIRFSOC_I2C_STATUS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SIRFSOC_I2C_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SIRFSOC_I2C_IO_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SIRFSOC_I2C_SDA_DELAY 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SIRFSOC_I2C_CMD_START 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SIRFSOC_I2C_CMD_BUF 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIRFSOC_I2C_DATA_BUF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIRFSOC_I2C_CMD_BUF_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIRFSOC_I2C_DATA_BUF_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SIRFSOC_I2C_DIV_MASK (0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* I2C status flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SIRFSOC_I2C_STAT_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SIRFSOC_I2C_STAT_TIP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIRFSOC_I2C_STAT_NACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIRFSOC_I2C_STAT_TR_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SIRFSOC_I2C_STAT_STOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIRFSOC_I2C_STAT_CMD_DONE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIRFSOC_I2C_STAT_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIRFSOC_I2C_CMD_INDEX (0x1F<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* I2C control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SIRFSOC_I2C_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIRFSOC_I2C_CORE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIRFSOC_I2C_MASTER_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SIRFSOC_I2C_CMD_DONE_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIRFSOC_I2C_ERR_INT_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIRFSOC_I2C_SCLF_FILTER (3<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIRFSOC_I2C_START_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIRFSOC_I2C_NACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SIRFSOC_I2C_WRITE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SIRFSOC_I2C_READ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SIRFSOC_I2C_STOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SIRFSOC_I2C_START BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SIRFSOC_I2C_ERR_NOACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIRFSOC_I2C_ERR_TIMEOUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sirfsoc_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 cmd_ptr; /* Current position in CMD buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 *buf; /* Buffer passed by user */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 msg_len; /* Message length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 finished_len; /* number of bytes read/written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 read_cmd_len; /* number of read cmd sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int msg_read; /* 1 indicates a read message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int err_status; /* 1 indicates an error on bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 sda_delay; /* For suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int last; /* Last message in transfer, STOP cmd can be sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct completion done; /* indicates completion of message transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < siic->read_cmd_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!(i & 0x3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) siic->buf[siic->finished_len++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SIRFSOC_I2C_DATA_SHIFT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (siic->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) while (((siic->finished_len + i) < siic->msg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (((siic->finished_len + i) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (siic->msg_len - 1)) && siic->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) siic->read_cmd_len = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) && (siic->finished_len < siic->msg_len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((siic->finished_len == (siic->msg_len - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) && siic->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regval |= SIRFSOC_I2C_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel(siic->buf[siic->finished_len++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) siic->cmd_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Trigger the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (i2c_stat & SIRFSOC_I2C_STAT_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Error conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) siic->err_status = SIRFSOC_I2C_ERR_NOACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (i2c_stat & SIRFSOC_I2C_STAT_NACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_dbg(&siic->adapter.dev, "ACK not received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&siic->adapter.dev, "I2C error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Due to hardware ANOMALY, we need to reset I2C earlier after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * we get NOACK while accessing non-existing clients, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * we will get errors even we access existing clients later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) complete(&siic->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* CMD buffer execution complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (siic->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) i2c_sirfsoc_read_data(siic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (siic->finished_len == siic->msg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) complete(&siic->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else /* Fill a new CMD buffer for left data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) i2c_sirfsoc_queue_cmd(siic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* no data and last message -> add STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (siic->last && (msg->len == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) regval |= SIRFSOC_I2C_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Reverse direction bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (msg->flags & I2C_M_REV_DIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) addr ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* timeout waiting for the xfer to finish or fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int timeout = msecs_to_jiffies((msg->len + 1) * 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i2c_sirfsoc_set_address(siic, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) i2c_sirfsoc_queue_cmd(siic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (wait_for_completion_timeout(&siic->done, timeout) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(&siic->adapter.dev, "Transfer timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(0, siic->base + SIRFSOC_I2C_CMD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* i2c control doesn't response, reset it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return siic->err_status ? -EAGAIN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static u32 i2c_sirfsoc_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sirfsoc_i2c *siic = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk_enable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) siic->buf = msgs[i].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) siic->msg_len = msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) siic->msg_read = !!(msgs[i].flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) siic->err_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) siic->cmd_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) siic->finished_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) siic->last = (i == (num - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) clk_disable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) clk_disable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* I2C algorithms associated with this master controller driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct i2c_algorithm i2c_sirfsoc_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .master_xfer = i2c_sirfsoc_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .functionality = i2c_sirfsoc_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int i2c_sirfsoc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct sirfsoc_i2c *siic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ctrl_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(&pdev->dev, "Clock get failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err_get_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err = clk_prepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(&pdev->dev, "Clock prepare failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto err_clk_prep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) err = clk_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(&pdev->dev, "Clock enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goto err_clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ctrl_speed = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!siic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) adap = &siic->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) siic->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (IS_ERR(siic->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err = PTR_ERR(siic->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_name(&pdev->dev), siic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) adap->algo = &i2c_sirfsoc_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) adap->algo_data = siic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) platform_set_drvdata(pdev, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) init_completion(&siic->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Controller initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) siic->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) err = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "clock-frequency", &bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bitrate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Due to some hardware design issues, we need to tune the formula.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Since i2c is open drain interface that allows the slave to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * stall the transaction by holding the SCL line at '0', the RTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * implementation is waiting for SCL feedback from the pin after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * setting it to High-Z ('1'). This wait adds to the high-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * interval counter few cycles of the input synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * (depending on the SCL_FILTER_REG field), and also the time it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * takes for the board pull-up resistor to rise the SCL line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * For slow SCL settings these additions are negligible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * but they start to affect the speed when clock is set to faster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Through the actual tests, use the different user_div value(which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * in the divider formula 'Fio / (Fi2c * user_div)') to adapt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * the different ranges of i2c bus clock frequency, to make the SCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * more accurate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (bitrate <= 30000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regval = ctrl_speed / (bitrate * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else if (bitrate > 30000 && bitrate <= 280000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) regval = (2 * ctrl_speed) / (bitrate * 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) regval = ctrl_speed / (bitrate * 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (regval > 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_info(&pdev->dev, " I2C adapter ready to operate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err_clk_en:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err_clk_prep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err_get_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int i2c_sirfsoc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct i2c_adapter *adapter = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct sirfsoc_i2c *siic = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) i2c_del_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) clk_unprepare(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk_put(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int i2c_sirfsoc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct i2c_adapter *adapter = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sirfsoc_i2c *siic = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clk_enable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk_disable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int i2c_sirfsoc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct i2c_adapter *adapter = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct sirfsoc_i2c *siic = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk_enable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) siic->base + SIRFSOC_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_disable(siic->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct dev_pm_ops i2c_sirfsoc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .suspend = i2c_sirfsoc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .resume = i2c_sirfsoc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct of_device_id sirfsoc_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { .compatible = "sirf,prima2-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static struct platform_driver i2c_sirfsoc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .name = "sirfsoc_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .pm = &i2c_sirfsoc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .of_match_table = sirfsoc_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .probe = i2c_sirfsoc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .remove = i2c_sirfsoc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) module_platform_driver(i2c_sirfsoc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DESCRIPTION("SiRF SoC I2C master controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_AUTHOR("Xiangzhen Ye <Xiangzhen.Ye@csr.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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