^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004 Steven J. Hill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2001,2002,2003 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995-2000 Simon G. Vogl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/sibyte/sb1250_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/sibyte/sb1250_smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct i2c_algo_sibyte_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void *data; /* private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int bus; /* which bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void *reg_base; /* CSR base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* ----- global defines ----------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMB_CSR(a,r) ((long)(a->reg_base + r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int smbus_xfer(struct i2c_adapter *i2c_adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 command, int size, union i2c_smbus_data * data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int data_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) csr_out32((V_SMB_ADDR(addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (read_write == I2C_SMBUS_READ ? M_SMB_QDATA : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) V_SMB_TT_QUICKCMD), SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_RD1BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) data_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR1BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD1BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) data_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) csr_out32(V_SMB_LB(data->byte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SMB_CSR(adap, R_SMB_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) csr_out32(V_SMB_CMD(command), SMB_CSR(adap, R_SMB_CMD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_CMD_RD2BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) data_bytes = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) csr_out32(V_SMB_LB(data->word & 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SMB_CSR(adap, R_SMB_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) csr_out32(V_SMB_MB(data->word >> 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SMB_CSR(adap, R_SMB_DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) csr_out32((V_SMB_ADDR(addr) | V_SMB_TT_WR2BYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SMB_CSR(adap, R_SMB_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) while (csr_in32(SMB_CSR(adap, R_SMB_STATUS)) & M_SMB_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) error = csr_in32(SMB_CSR(adap, R_SMB_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (error & M_SMB_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Clear error bit by writing a 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) csr_out32(M_SMB_ERROR, SMB_CSR(adap, R_SMB_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return (error & M_SMB_ERROR_TYPE) ? -EIO : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (data_bytes == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) data->byte = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (data_bytes == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data->word = csr_in32(SMB_CSR(adap, R_SMB_DATA)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u32 bit_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* -----exported algorithm data: ------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct i2c_algorithm i2c_sibyte_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .smbus_xfer = smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .functionality = bit_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * registering functions to load algorithms at runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int __init i2c_sibyte_add_bus(struct i2c_adapter *i2c_adap, int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_algo_sibyte_data *adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Register new adapter to i2c module... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) i2c_adap->algo = &i2c_sibyte_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Set the requested frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) csr_out32(speed, SMB_CSR(adap,R_SMB_FREQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) csr_out32(0, SMB_CSR(adap,R_SMB_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return i2c_add_numbered_adapter(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct i2c_algo_sibyte_data sibyte_board_data[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { NULL, 0, (void *) (CKSEG1+A_SMB_BASE(0)) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { NULL, 1, (void *) (CKSEG1+A_SMB_BASE(1)) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct i2c_adapter sibyte_board_adapter[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .algo = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .algo_data = &sibyte_board_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .nr = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "SiByte SMBus 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .algo = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .algo_data = &sibyte_board_data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .nr = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "SiByte SMBus 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int __init i2c_sibyte_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pr_info("i2c-sibyte: i2c SMBus adapter module for SiByte board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (i2c_sibyte_add_bus(&sibyte_board_adapter[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) K_SMB_FREQ_400KHZ) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) i2c_del_adapter(&sibyte_board_adapter[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __exit i2c_sibyte_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) i2c_del_adapter(&sibyte_board_adapter[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) i2c_del_adapter(&sibyte_board_adapter[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) module_init(i2c_sibyte_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) module_exit(i2c_sibyte_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_AUTHOR("Kip Walker (Broadcom Corp.)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DESCRIPTION("SMBus adapter routines for SiByte boards");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags