^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH Mobile I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Portions of the code based on out-of-tree driver i2c-sh7343.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Transmit operation: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* 0 byte transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* BUS: S A8 ACK P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* IRQ: DTE WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ICIC: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* ICCR: 0x94 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* ICDR: A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 1 byte transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* BUS: S A8 ACK D8(1) ACK P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* IRQ: DTE WAIT WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* ICIC: -DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* ICCR: 0x94 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* ICDR: A8 D8(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 2 byte transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* IRQ: DTE WAIT WAIT WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* ICIC: -DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ICCR: 0x94 0x90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* ICDR: A8 D8(1) D8(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* 3 bytes or more, +---------+ gets repeated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Receive operation: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 0 byte receive - not supported since slave may hold SDA low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* 1 byte receive [TX] | [RX] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* BUS: S A8 ACK | D8(1) ACK P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* IRQ: DTE WAIT | WAIT DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* ICIC: -DTE | +DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ICCR: 0x94 0x81 | 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ICDR: A8 | D8(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 2 byte receive [TX]| [RX] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* IRQ: DTE WAIT | WAIT WAIT DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* ICIC: -DTE | +DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* ICCR: 0x94 0x81 | 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* ICDR: A8 | D8(1) D8(2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* 3 byte receive [TX] | [RX] (*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* ICIC: -DTE | +DTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ICCR: 0x94 0x81 | 0xc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* ICDR: A8 | D8(1) D8(2) D8(3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 4 bytes or more, this part is repeated +---------+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Interrupt order and BUSY flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* ___ _ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* ___ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* WAIT IRQ ________________________________/ \___________ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* TACK IRQ ____________________________________/ \_______ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* DTE IRQ __________________________________________/ \_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* _______________________________________________ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* BUSY __/ \_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* (*) The STOP condition is only sent by the master at the end of the last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* only cleared after the STOP condition, so, between messages we have to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* poll for the DTE bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum sh_mobile_i2c_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) OP_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) OP_TX_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) OP_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) OP_TX_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) OP_TX_TO_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) OP_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) OP_RX_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) OP_RX_STOP_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct sh_mobile_i2c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int clks_per_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u_int8_t icic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u_int8_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u_int16_t iccl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u_int16_t icch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bool send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool stop_after_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool atomic_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum dma_data_direction dma_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct sh_mobile_dt_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int clks_per_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int (*setup)(struct sh_mobile_i2c_data *pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IIC_FLAG_HAS_ICIC67 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ICDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ICCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ICSR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ICIC 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ICCL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ICCH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ICSTART 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ICCR_ICE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ICCR_RACK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ICCR_TRS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ICCR_BBSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ICCR_SCP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ICSR_SCLM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ICSR_SDAM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SW_DONE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ICSR_BUSY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ICSR_AL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ICSR_TACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ICSR_WAIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ICSR_DTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ICIC_ICCLB8 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ICIC_ICCHB8 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ICIC_TDMAE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ICIC_RDMAE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ICIC_ALE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ICIC_TACKE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ICIC_WAITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ICIC_DTEE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ICSTART_ICSTART 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (offs == ICIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) data |= pd->icic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) iowrite8(data, pd->reg + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ioread8(pd->reg + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned char set, unsigned char clr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Conditional expression:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * ICCL >= COUNT_CLK * (tLOW + tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * SH-Mobile IIC hardware starts counting the LOW period of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * the SCL signal (tLOW) as soon as it pulls the SCL line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * In order to meet the tLOW timing spec, we need to take into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * account the fall time of SCL signal (tf). Default tf value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * should be 0.3 us, for safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return (((count_khz * (tLOW + tf)) + 5000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Conditional expression:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * ICCH >= COUNT_CLK * (tHIGH + tf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * and can ignore it. SH-Mobile IIC controller starts counting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * the HIGH period of the SCL signal (tHIGH) after the SCL input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * voltage increases at VIH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Afterward it turned out calculating ICCH using only tHIGH spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * will result in violation of the tHD;STA timing spec. We need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * to take into account the fall time of SDA signal (tf) at START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * condition, in order to meet both tHIGH and tHD;STA specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (pd->iccl > max_val || pd->icch > max_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pd->iccl, pd->icch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* one more bit of ICCL in ICIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (pd->iccl & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pd->icic |= ICIC_ICCLB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pd->icic &= ~ICIC_ICCLB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* one more bit of ICCH in ICIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (pd->icch & 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pd->icic |= ICIC_ICCHB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pd->icic &= ~ICIC_ICCHB8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long i2c_clk_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 tHIGH, tLOW, tf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (pd->bus_speed == I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) tLOW = 47; /* tLOW = 4.7 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) tf = 3; /* tf = 0.3 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else if (pd->bus_speed == I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tLOW = 13; /* tLOW = 1.3 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tf = 3; /* tf = 0.3 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pd->bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return sh_mobile_i2c_check_timing(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned long clks_per_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* L = 5, H = 4, L + H = 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return sh_mobile_i2c_check_timing(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static unsigned char i2c_op(struct sh_mobile_i2c_data *pd, enum sh_mobile_i2c_op op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned char ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_dbg(pd->dev, "op %d\n", op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spin_lock_irqsave(&pd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case OP_START: /* issue start and trigger DTE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case OP_TX_FIRST: /* disable DTE interrupt and write client address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) iic_wr(pd, ICDR, i2c_8bit_addr_from_msg(pd->msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case OP_TX: /* write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) iic_wr(pd, ICDR, pd->msg->buf[pd->pos]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case OP_TX_STOP: /* issue a stop (or rep_start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case OP_TX_TO_RX: /* select read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case OP_RX: /* just read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = iic_rd(pd, ICDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case OP_RX_STOP: /* enable DTE interrupt, issue stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!pd->atomic_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iic_wr(pd, ICIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!pd->atomic_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) iic_wr(pd, ICIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = iic_rd(pd, ICDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) spin_unlock_irqrestore(&pd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (pd->pos == pd->msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) i2c_op(pd, OP_TX_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (pd->pos == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c_op(pd, OP_TX_FIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) i2c_op(pd, OP_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pd->pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int real_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* switch from TX (address) to RX (data) adds two interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) real_pos = pd->pos - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (pd->pos == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i2c_op(pd, OP_TX_FIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } else if (pd->pos == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) i2c_op(pd, OP_TX_TO_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else if (pd->pos == pd->msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (pd->stop_after_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Simulate PIO end condition after DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) i2c_op(pd, OP_RX_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pd->pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (real_pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_op(pd, OP_RX_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pd->msg->buf[real_pos] = i2c_op(pd, OP_RX_STOP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else if (real_pos >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pd->msg->buf[real_pos] = i2c_op(pd, OP_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pd->pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return pd->pos == (pd->msg->len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct sh_mobile_i2c_data *pd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned char sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int wakeup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sr = iic_rd(pd, ICSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pd->sr |= sr; /* remember state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) (pd->msg->flags & I2C_M_RD) ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pd->pos, pd->msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Kick off TxDMA after preface was done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else if (sr & (ICSR_AL | ICSR_TACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* don't interrupt transaction - continue to issue stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) else if (pd->msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) wakeup = sh_mobile_i2c_isr_rx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) wakeup = sh_mobile_i2c_isr_tx(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Kick off RxDMA after preface was done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pd->sr |= SW_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!pd->atomic_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wake_up(&pd->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* defeat write posting to avoid spurious WAIT interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) iic_rd(pd, ICSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ? pd->dma_rx : pd->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pd->msg->len, pd->dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pd->dma_direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (pd->dma_direction == DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else if (pd->dma_direction == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dmaengine_terminate_all(pd->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) else if (pd->dma_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dmaengine_terminate_all(pd->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sh_mobile_i2c_dma_unmap(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void sh_mobile_i2c_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sh_mobile_i2c_data *pd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sh_mobile_i2c_dma_unmap(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pd->pos = pd->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pd->stop_after_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) enum dma_transfer_direction dir, dma_addr_t port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) chan = dma_request_chan(dev, chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PTR_ERR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cfg.direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cfg.dst_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cfg.src_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_dbg(dev, "got DMA channel for %s\n", chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bool read = pd->msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (PTR_ERR(chan) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pd->res->start + ICDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pd->res->start + ICDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (IS_ERR(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (dma_mapping_error(chan->device->dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_dbg(pd->dev, "dma map failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sg_dma_len(&pd->sg) = pd->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) sg_dma_address(&pd->sg) = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pd->dma_direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!txdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) sh_mobile_i2c_cleanup_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) txdesc->callback = sh_mobile_i2c_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) txdesc->callback_param = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cookie = dmaengine_submit(txdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (dma_submit_error(cookie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sh_mobile_i2c_cleanup_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) bool do_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (do_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Initialize channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) iic_wr(pd, ICCR, ICCR_SCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Enable channel and configure rx ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Set the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) iic_wr(pd, ICCL, pd->iccl & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) iic_wr(pd, ICCH, pd->icch & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pd->msg = usr_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pd->pos = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pd->sr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (pd->atomic_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (pd->dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) sh_mobile_i2c_xfer_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Enable all interrupts to begin with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int poll_dte(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 1000; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u_int8_t val = iic_rd(pd, ICSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (val & ICSR_DTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (val & ICSR_TACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return i ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int poll_busy(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) for (i = 1000; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u_int8_t val = iic_rd(pd, ICSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* the interrupt handler may wake us up before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * transfer is finished, so poll the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * until we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!(val & ICSR_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* handle missing acknowledge and arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val |= pd->sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (val & ICSR_TACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (val & ICSR_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return i ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int sh_mobile_xfer(struct sh_mobile_i2c_data *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Wake up device and enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pm_runtime_get_sync(pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Process all messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) bool do_start = pd->send_stop || !i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) msg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pd->stop_after_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) start_ch(pd, msg, do_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (do_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) i2c_op(pd, OP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (pd->atomic_xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned long j = jiffies + pd->adap.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) time_left = time_before_eq(jiffies, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) while (time_left &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) !(pd->sr & (ICSR_TACK | SW_DONE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned char sr = iic_rd(pd, ICSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (sr & (ICSR_AL | ICSR_TACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ICSR_WAIT | ICSR_DTE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) sh_mobile_i2c_isr(0, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) udelay(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) time_left = time_before_eq(jiffies, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* The interrupt handler takes care of the rest... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) time_left = wait_event_timeout(pd->wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pd->sr & (ICSR_TACK | SW_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pd->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* 'stop_after_dma' tells if DMA xfer was complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pd->stop_after_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(pd->dev, "Transfer request timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (pd->dma_direction != DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sh_mobile_i2c_cleanup_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (pd->send_stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) err = poll_busy(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err = poll_dte(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Disable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) iic_wr(pd, ICCR, ICCR_SCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Disable clock and mark device as idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pm_runtime_put_sync(pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return err ?: num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pd->atomic_xfer = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return sh_mobile_xfer(pd, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int sh_mobile_i2c_xfer_atomic(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pd->atomic_xfer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return sh_mobile_xfer(pd, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .functionality = sh_mobile_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .master_xfer = sh_mobile_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .master_xfer_atomic = sh_mobile_i2c_xfer_atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .flags = I2C_AQ_NO_ZERO_LEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * r8a7740 has an errata regarding I2C I/O pad reset needing this workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) iic_set_clr(pd, ICCR, ICCR_ICE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) iic_rd(pd, ICCR); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) iic_rd(pd, ICSTART); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) iic_wr(pd, ICCR, ICCR_SCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) iic_wr(pd, ICSTART, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) iic_wr(pd, ICCR, ICCR_TRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) iic_wr(pd, ICCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) iic_wr(pd, ICCR, ICCR_TRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return sh_mobile_i2c_init(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct sh_mobile_dt_config default_dt_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .clks_per_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .setup = sh_mobile_i2c_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct sh_mobile_dt_config fast_clock_dt_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .clks_per_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .setup = sh_mobile_i2c_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .clks_per_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .setup = sh_mobile_i2c_v2_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const struct sh_mobile_dt_config r8a7740_dt_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .clks_per_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .setup = sh_mobile_i2c_r8a7740_workaround,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { .compatible = "renesas,iic-r8a774c0", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { .compatible = "renesas,iic-r8a7791", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { .compatible = "renesas,iic-r8a7792", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) { .compatible = "renesas,iic-r8a7793", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { .compatible = "renesas,iic-r8a7794", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { .compatible = "renesas,iic-r8a7795", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { .compatible = "renesas,iic-r8a77990", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .compatible = "renesas,rcar-gen2-iic", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .compatible = "renesas,rcar-gen3-iic", .data = &v2_freq_calc_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!IS_ERR(pd->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) dma_release_channel(pd->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!IS_ERR(pd->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dma_release_channel(pd->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) resource_size_t n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int k = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) for (n = res->start; n <= res->end; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 0, dev_name(&dev->dev), pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) k++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return k > 0 ? 0 : -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int sh_mobile_i2c_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct sh_mobile_i2c_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) const struct sh_mobile_dt_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u32 bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) pd->clk = devm_clk_get(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (IS_ERR(pd->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(&dev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return PTR_ERR(pd->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = sh_mobile_i2c_hook_irqs(dev, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pd->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) platform_set_drvdata(dev, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) pd->res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pd->reg = devm_ioremap_resource(&dev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (IS_ERR(pd->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return PTR_ERR(pd->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pd->bus_speed = (ret || !bus_speed) ? I2C_MAX_STANDARD_MODE_FREQ : bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pd->clks_per_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Newer variants come with two new bits in ICIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (resource_size(res) > 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pd->flags |= IIC_FLAG_HAS_ICIC67;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pm_runtime_enable(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pm_runtime_get_sync(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) config = of_device_get_match_data(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pd->clks_per_count = config->clks_per_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = config->setup(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = sh_mobile_i2c_init(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pm_runtime_put_sync(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Init DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) sg_init_table(&pd->sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pd->dma_direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* setup the private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) adap = &pd->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) i2c_set_adapdata(adap, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) adap->algo = &sh_mobile_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) adap->quirks = &sh_mobile_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) adap->dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) adap->retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) adap->nr = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) adap->dev.of_node = dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) strlcpy(adap->name, dev->name, sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) spin_lock_init(&pd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) init_waitqueue_head(&pd->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) sh_mobile_i2c_release_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int sh_mobile_i2c_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) i2c_del_adapter(&pd->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sh_mobile_i2c_release_dma(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pm_runtime_disable(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static struct platform_driver sh_mobile_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .name = "i2c-sh_mobile",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .of_match_table = sh_mobile_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .probe = sh_mobile_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .remove = sh_mobile_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int __init sh_mobile_i2c_adap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return platform_driver_register(&sh_mobile_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) subsys_initcall(sh_mobile_i2c_adap_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static void __exit sh_mobile_i2c_adap_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) platform_driver_unregister(&sh_mobile_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) module_exit(sh_mobile_i2c_adap_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MODULE_AUTHOR("Wolfram Sang");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) MODULE_ALIAS("platform:i2c-sh_mobile");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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