^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* linux/drivers/i2c/busses/i2c-s3c2410.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004,2005,2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * S3C2410 I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_IICCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C2410_IICSTAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2410_IICADD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2410_IICDS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C2440_IICLC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_IICCON_ACKEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2410_IICCON_TXDIV_16 (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_IICCON_TXDIV_512 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_IICCON_IRQEN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_IICCON_IRQPEND (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_IICCON_SCALEMASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C2410_IICSTAT_MODEMASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2410_IICSTAT_START (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2410_IICSTAT_TXRXEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C2410_IICSTAT_ARBITR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2410_IICSTAT_ADDR0 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C2410_IICSTAT_LASTBIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C2410_IICLC_FILTER_ON (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QUIRK_S3C2440 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QUIRK_HDMIPHY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QUIRK_NO_GPIO (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QUIRK_POLL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Max time to wait for bus to become idle after a xfer (in us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C2410_IDLE_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Exynos5 Sysreg offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EXYNOS5_SYS_I2C_CFG 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* i2c controller state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) enum s3c24xx_i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) STATE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) STATE_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) STATE_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) STATE_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct s3c24xx_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) kernel_ulong_t quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int tx_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum s3c24xx_i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct s3c2410_platform_i2c *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct gpio_desc *gpios[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct notifier_block freq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regmap *sysreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int sys_i2c_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct platform_device_id s3c24xx_driver_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "s3c2410-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .driver_data = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "s3c2440-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .driver_data = QUIRK_S3C2440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "s3c2440-hdmiphy-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct of_device_id s3c24xx_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .compatible = "samsung,s3c2440-hdmiphy-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .compatible = "samsung,exynos5-sata-phy-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Get controller type either from device tree or platform device variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return (kernel_ulong_t)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Complete the message and wake up the caller, using the given return code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * or zero to mean ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(i2c->dev, "master_complete %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) i2c->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) i2c->msg_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) i2c->msg_idx = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!(i2c->quirks & QUIRK_POLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) wake_up(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* irq enable/disable functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static bool is_ack(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (tries = 50; tries; --tries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (readl(i2c->regs + S3C2410_IICCON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) & S3C2410_IICCON_IRQPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!(readl(i2c->regs + S3C2410_IICSTAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) & S3C2410_IICSTAT_LASTBIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(i2c->dev, "ack was not received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * put the start of a message onto the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int addr = (msg->addr & 0x7f) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long iiccon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) stat |= S3C2410_IICSTAT_TXRXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) stat |= S3C2410_IICSTAT_MASTER_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) addr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) stat |= S3C2410_IICSTAT_MASTER_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (msg->flags & I2C_M_REV_DIR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) addr ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* todo - check for whether ack wanted or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) s3c24xx_i2c_enable_ack(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) iiccon = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(stat, i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writeb(addr, i2c->regs + S3C2410_IICDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * delay here to ensure the data byte has gotten onto the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * before the transaction is started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ndelay(i2c->tx_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(iiccon, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) stat |= S3C2410_IICSTAT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(stat, i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (i2c->quirks & QUIRK_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while ((i2c->msg_num != 0) && is_ack(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) i2c_s3c_irq_nextbyte(i2c, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) stat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (stat & S3C2410_IICSTAT_ARBITR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(i2c->dev, "deal with arbitration loss\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(i2c->dev, "STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * The datasheet says that the STOP sequence should be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * 2) I2CCON.4 = 0 - Clear IRQPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * 3) Wait until the stop condition takes effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * However, after much experimentation, it appears that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * a) normal buses automatically clear BUSY and transition from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Master->Slave when they complete generating a STOP condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * after starting the STOP generation here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * b) HDMIPHY bus does neither, so there is no way to do step 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * There is no indication when this bus has finished generating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * STOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * In fact, we have found that as soon as the IRQPEND bit is cleared in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * step 2, the HDMIPHY bus generates the STOP condition, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * immediately starts transferring another data byte, even though the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * bus is supposedly stopped. This is presumably because the bus is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * still in "Master" mode, and its BUSY bit is still set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * To avoid these extra post-STOP transactions on HDMI phy devices, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * instead of first generating a proper STOP condition. This should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * float SDA & SCK terminating the transfer. Subsequent transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * start with a proper START condition, and proceed normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * The HDMIPHY bus is an internal bus that always has exactly two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * devices, the host as Master and the HDMIPHY device as the slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Skipping the STOP condition has been tested on this bus and works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (i2c->quirks & QUIRK_HDMIPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Stop driving the I2C pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) iicstat &= ~S3C2410_IICSTAT_TXRXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* stop the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) iicstat &= ~S3C2410_IICSTAT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(iicstat, i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) i2c->state = STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) s3c24xx_i2c_master_complete(i2c, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) s3c24xx_i2c_disable_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * helper functions to determine the current state in the set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * messages we are sending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * returns TRUE if the current message is the last in the set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return i2c->msg_idx >= (i2c->msg_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * returns TRUE if we this is the last byte in the current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline int is_msglast(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * msg->len is always 1 for the first byte of smbus block read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Actual length will be read from slave. More bytes will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * read according to the length then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return i2c->msg_ptr == i2c->msg->len-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * returns TRUE if we reached the end of the current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static inline int is_msgend(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return i2c->msg_ptr >= i2c->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * process an interrupt and work out what to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (i2c->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case STATE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case STATE_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) s3c24xx_i2c_disable_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto out_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case STATE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * last thing we did was send a start condition on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * bus, or started a new i2c message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (iicstat & S3C2410_IICSTAT_LASTBIT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* ack was not received... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_dbg(i2c->dev, "ack was not received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) s3c24xx_i2c_stop(i2c, -ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) goto out_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (i2c->msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i2c->state = STATE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) i2c->state = STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Terminate the transfer if there is nothing to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * as this is used by the i2c probe to find devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (is_lastmsg(i2c) && i2c->msg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) s3c24xx_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto out_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (i2c->state == STATE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto prepare_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * fall through to the write state, as we will need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * send a byte as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case STATE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * we are writing data to the device... check for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * end of the message, and if so, work out what to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (iicstat & S3C2410_IICSTAT_LASTBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_dbg(i2c->dev, "WRITE: No Ack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto out_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) retry_write:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!is_msgend(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) byte = i2c->msg->buf[i2c->msg_ptr++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) writeb(byte, i2c->regs + S3C2410_IICDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * delay after writing the byte to allow the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * data setup time on the bus, as writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * data to the register causes the first bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * to appear on SDA, and SCL will change as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * soon as the interrupt is acknowledged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ndelay(i2c->tx_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) } else if (!is_lastmsg(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* we need to go to the next i2c message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_dbg(i2c->dev, "WRITE: Next Message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) i2c->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* check to see if we need to do another message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (i2c->msg->flags & I2C_M_NOSTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (i2c->msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * cannot do this, the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * forces us to send a new START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * when we change direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "missing START before write->read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) s3c24xx_i2c_stop(i2c, -EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto retry_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* send the new start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) s3c24xx_i2c_message_start(i2c, i2c->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* send stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) s3c24xx_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case STATE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * we have a byte of data in the data register, do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * something with it, and then work out whether we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * going to do any more read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) byte = readb(i2c->regs + S3C2410_IICDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2c->msg->buf[i2c->msg_ptr++] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Add actual length to read for smbus block read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) i2c->msg->len += byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) prepare_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (is_msglast(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* last byte of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (is_lastmsg(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) s3c24xx_i2c_disable_ack(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else if (is_msgend(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * ok, we've read the entire buffer, see if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * is anything else we need to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (is_lastmsg(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* last message, send stop and complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(i2c->dev, "READ: Send Stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) s3c24xx_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* go to the next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_dbg(i2c->dev, "READ: Next Transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) i2c->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* acknowlegde the IRQ and get back on with the work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) out_ack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) tmp &= ~S3C2410_IICCON_IRQPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(tmp, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * top level IRQ servicing routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct s3c24xx_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) status = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (status & S3C2410_IICSTAT_ARBITR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* deal with arbitration loss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(i2c->dev, "deal with arbitration loss\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (i2c->state == STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tmp &= ~S3C2410_IICCON_IRQPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) writel(tmp, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * pretty much this leaves us with the fact that we've
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * transmitted or received whatever byte we last sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) i2c_s3c_irq_nextbyte(i2c, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Disable the bus so that we won't get any interrupts from now on, or try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * to drive any lines. This is the default state when we don't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * anything to send/receive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * If there is an event on the bus, or we have a pre-existing event at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * kernel boot time, we may not notice the event and the I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * will lock the bus with the I2C clock line low indefinitely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Stop driving the I2C pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tmp = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tmp &= ~S3C2410_IICSTAT_TXRXEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) writel(tmp, i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* We don't expect any interrupts now, and don't want send acks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tmp = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) S3C2410_IICCON_ACKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) writel(tmp, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * get the i2c bus for a master transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned long iicstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int timeout = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) while (timeout-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) iicstat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * wait for the i2c bus to become idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned long iicstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ktime_t start, now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int spins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* ensure the stop has been through the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_dbg(i2c->dev, "waiting for bus idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) start = now = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Most of the time, the bus is already idle within a few usec of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * end of a transaction. However, really slow i2c devices can stretch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * the clock, delaying STOP generation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * On slower SoCs this typically happens within a very small number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * instructions so busy wait briefly to avoid scheduling overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spins = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) iicstat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iicstat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * If we do get an appreciable delay as a compromise between idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * detection latency for the normal, fast case, and system load in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * slow device case, use an exponential back off in the polling loop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * up to 1/10th of the total timeout, then continue to poll at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * constant rate up to the timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) while ((iicstat & S3C2410_IICSTAT_START) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) usleep_range(delay, 2 * delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (delay < S3C2410_IDLE_TIMEOUT / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) delay <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) now = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) iicstat = readl(i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (iicstat & S3C2410_IICSTAT_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_warn(i2c->dev, "timeout waiting for bus idle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * this starts an i2c transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = s3c24xx_i2c_set_master(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) i2c->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) i2c->msg_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) i2c->msg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) s3c24xx_i2c_enable_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) s3c24xx_i2c_message_start(i2c, msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (i2c->quirks & QUIRK_POLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = i2c->msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret != num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = i2c->msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Having these next two as dev_err() makes life very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * noisy when doing an i2cdetect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(i2c->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else if (ret != num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* For QUIRK_HDMIPHY, bus is already disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (i2c->quirks & QUIRK_HDMIPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) s3c24xx_i2c_wait_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) s3c24xx_i2c_disable_bus(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * first port of call from the i2c bus code when an message needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * transferring across the i2c bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) for (retry = 0; retry < adap->retries; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret != -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* declare our i2c functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* i2c bus registration info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .master_xfer = s3c24xx_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .functionality = s3c24xx_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * return the divisor settings for a given frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned int *div1, unsigned int *divs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned int calc_divs = clkin / wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) unsigned int calc_div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (calc_divs > (16*16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) calc_div1 = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) calc_div1 = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) calc_divs += calc_div1-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) calc_divs /= calc_div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (calc_divs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) calc_divs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (calc_divs > 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) calc_divs = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *divs = calc_divs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) *div1 = calc_div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return clkin / (calc_divs * calc_div1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * work out a divisor for the user requested frequency setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * either by the requested frequency, or scanning the acceptable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * range of frequencies until something is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct s3c2410_platform_i2c *pdata = i2c->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned long clkin = clk_get_rate(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) unsigned int divs, div1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) unsigned long target_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 iiccon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) i2c->clkrate = clkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clkin /= 1000; /* clkin now in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) target_frequency /= 1000; /* Target frequency now in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (freq > target_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "Unable to achieve desired frequency %luKHz." \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) " Lowest achievable %dKHz\n", target_frequency, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) *got = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) iiccon = readl(i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) iiccon |= (divs-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (div1 == 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) iiccon |= S3C2410_IICCON_TXDIV_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (i2c->quirks & QUIRK_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) iiccon |= S3C2410_IICCON_SCALE(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) writel(iiccon, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (i2c->quirks & QUIRK_S3C2440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned long sda_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (pdata->sda_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) sda_delay = clkin * pdata->sda_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) sda_delay = DIV_ROUND_UP(sda_delay, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (sda_delay > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) sda_delay = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) sda_delay |= S3C2410_IICLC_FILTER_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) sda_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) writel(sda_delay, i2c->regs + S3C2440_IICLC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) unsigned long val, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned int got;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int delta_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* if we're post-change and the input clock has slowed down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * or at pre-change and the clock is about to speed up, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * adjust our clock rate. <0 is slow, >0 speedup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = s3c24xx_i2c_clockrate(i2c, &got);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_info(i2c->dev, "setting freq %d\n", got);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return cpufreq_register_notifier(&i2c->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) cpufreq_unregister_notifier(&i2c->freq_transition,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (i2c->quirks & QUIRK_NO_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) i, GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (IS_ERR(i2c->gpios[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * initialise the controller, set the IO lines and frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct s3c2410_platform_i2c *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* get the plafrom data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pdata = i2c->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* write slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) writel(0, i2c->regs + S3C2410_IICCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) writel(0, i2c->regs + S3C2410_IICSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* we need to work out the divisors for the clock... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(i2c->dev, "cannot meet bus frequency required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* todo - check that the i2c lines aren't being dragged anywhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) readl(i2c->regs + S3C2410_IICCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * Parse the device tree node and retreive the platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct s3c2410_platform_i2c *pdata = i2c->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) of_property_read_u32(np, "samsung,i2c-max-bus-freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) (u32 *)&pdata->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * Exynos5's legacy i2c controller and new high speed i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * controller have muxed interrupt sources. By default the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * interrupts for 4-channel HS-I2C controller are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * If nodes for first four channels of legacy i2c controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * are available then re-configure the interrupts via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * system register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) id = of_alias_get_id(np, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) "samsung,sysreg-phandle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (IS_ERR(i2c->sysreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int s3c24xx_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct s3c24xx_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct s3c2410_platform_i2c *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_err(&pdev->dev, "no platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!i2c->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) i2c->quirks = s3c24xx_get_device_quirks(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) i2c->sysreg = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) memcpy(i2c->pdata, pdata, sizeof(*pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) i2c->adap.algo = &s3c24xx_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) i2c->adap.retries = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) i2c->adap.class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) i2c->tx_setup = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) init_waitqueue_head(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* find the clock and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) i2c->clk = devm_clk_get(&pdev->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* map the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) i2c->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (IS_ERR(i2c->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return PTR_ERR(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dev_dbg(&pdev->dev, "registers %p (%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) i2c->regs, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* setup info block for the i2c core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) i2c->adap.algo_data = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* inititalise the i2c gpio lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (i2c->pdata->cfg_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* initialise the i2c controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(&pdev->dev, "I2C clock enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = s3c24xx_i2c_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_err(&pdev->dev, "I2C controller init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * find the IRQ for this unit (note, this relies on the init call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * ensure no current IRQs pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!(i2c->quirks & QUIRK_POLL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) i2c->irq = ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_err(&pdev->dev, "cannot find IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) 0, dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = s3c24xx_i2c_register_cpufreq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Note, previous versions of the driver used i2c_add_adapter()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * to add the bus at any number. We now pass the bus number via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * the platform data, so if unset it will now default to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * being bus 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) i2c->adap.nr = i2c->pdata->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = i2c_add_numbered_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) s3c24xx_i2c_deregister_cpufreq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int s3c24xx_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) s3c24xx_i2c_deregister_cpufreq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int s3c24xx_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) i2c_mark_adapter_suspended(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!IS_ERR(i2c->sysreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int s3c24xx_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (!IS_ERR(i2c->sysreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret = clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) s3c24xx_i2c_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2c_mark_adapter_resumed(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) s3c24xx_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define S3C24XX_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static struct platform_driver s3c24xx_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .probe = s3c24xx_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .remove = s3c24xx_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .id_table = s3c24xx_driver_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .name = "s3c-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .pm = S3C24XX_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .of_match_table = of_match_ptr(s3c24xx_i2c_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int __init i2c_adap_s3c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return platform_driver_register(&s3c24xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) subsys_initcall(i2c_adap_s3c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void __exit i2c_adap_s3c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) platform_driver_unregister(&s3c24xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) module_exit(i2c_adap_s3c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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