^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for I2C adapter in Rockchip RK3xxx SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Max Schwarz <max.schwarz@online.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * based on the patches by Rockchip Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/math64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/soc/rockchip/rockchip_thunderboot_service.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_CON 0x00 /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_CLKDIV 0x04 /* clock divisor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_MRXCNT 0x14 /* number of bytes to be received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_IEN 0x18 /* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_IPD 0x1c /* interrupt pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_FCNT 0x20 /* finished count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_CON1 0x228 /* control register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Data buffer offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TXBUFFER_BASE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RXBUFFER_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* REG_CON bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_CON_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) REG_CON_MOD_TX = 0, /* transmit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) REG_CON_MOD_REGISTER_TX, /* select register and restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) REG_CON_MOD_RX, /* receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * register addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_CON_MOD(mod) ((mod) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_CON_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_CON_STOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) RK_I2C_VERSION0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) RK_I2C_VERSION1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) RK_I2C_VERSION5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_CON_VERSION GENMASK_ULL(24, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_CON_VERSION_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* REG_MRXADDR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* REG_IEN/REG_IPD bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_INT_BTF BIT(0) /* a byte was transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_INT_BRF BIT(1) /* a byte was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_INT_MBTF BIT(2) /* master data transmit finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_INT_MBRF BIT(3) /* master data receive finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_INT_START BIT(4) /* START condition generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_INT_STOP BIT(5) /* STOP condition generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_INT_NAKRCV BIT(6) /* NACK received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_INT_ALL 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Disable i2c all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IEN_ALL_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_CON1_AUTO_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_CON1_TRANSFER_AUTO_STOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_CON1_NACK_AUTO_STOP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WAIT_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * struct i2c_spec_values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @min_hold_start_ns: min hold time (repeated) START condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @min_low_ns: min LOW period of the SCL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @min_high_ns: min HIGH period of the SCL cloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @min_setup_start_ns: min set-up time for a repeated START conditio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @max_data_hold_ns: max data hold time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @min_data_setup_ns: min data set-up time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @min_setup_stop_ns: min set-up time for STOP condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @min_hold_buffer_ns: min bus free time between a STOP and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * START condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_spec_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long min_hold_start_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long min_low_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long min_setup_start_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long max_data_hold_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long min_data_setup_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long min_setup_stop_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long min_hold_buffer_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct i2c_spec_values standard_mode_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .min_hold_start_ns = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .min_low_ns = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .min_high_ns = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .min_setup_start_ns = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .max_data_hold_ns = 3450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .min_data_setup_ns = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .min_setup_stop_ns = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .min_hold_buffer_ns = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct i2c_spec_values fast_mode_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .min_hold_start_ns = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .min_low_ns = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .min_high_ns = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .min_setup_start_ns = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .max_data_hold_ns = 900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .min_data_setup_ns = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .min_setup_stop_ns = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .min_hold_buffer_ns = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct i2c_spec_values fast_mode_plus_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .min_hold_start_ns = 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .min_low_ns = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .min_high_ns = 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .min_setup_start_ns = 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .max_data_hold_ns = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .min_data_setup_ns = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .min_setup_stop_ns = 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .min_hold_buffer_ns = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * struct rk3x_i2c_calced_timings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @div_low: Divider output for low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @div_high: Divider output for high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @tuning: Used to adjust setup/hold data time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * setup/hold start time and setup stop time for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * v1's calc_timings, the tuning should all be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * for old hardware anyone using v0's calc_timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct rk3x_i2c_calced_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long div_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long div_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum rk3x_i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) STATE_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) STATE_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) STATE_STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * struct rk3x_i2c_soc_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @grf_offset: offset inside the grf regmap for setting the i2c type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @calc_timings: Callback function for i2c timing information calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct rk3x_i2c_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int grf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int (*calc_timings)(unsigned long, struct i2c_timings *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct rk3x_i2c_calced_timings *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * struct rk3x_i2c - private data of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @adap: corresponding I2C adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @dev: device for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @soc_data: related soc data struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @regs: virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @clk: function clk for rk3399 or function & Bus clks for others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @pclk: Bus clk for rk3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @clk_rate_nb: i2c clk rate change notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @t: I2C known timing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @lock: spinlock for the i2c bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @wait: the waitqueue to wait for i2c transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @busy: the condition for the event to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @msg: current i2c message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @addr: addr of i2c slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @mode: mode of i2c transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @is_last_msg: flag determines whether it is the last msg in this transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @state: state of i2c transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @processed: byte length which has been send or received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @error: error code for i2c transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @i2c_restart_nb: make sure the i2c transfer to be finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @system_restarting: true if system is restarting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @tb_cl: client for rockchip thunder boot service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct rk3x_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const struct rk3x_i2c_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Hardware resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct notifier_block clk_rate_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bool autostop_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct i2c_timings t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Synchronization & notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bool busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Current message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bool is_last_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* I2C state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum rk3x_i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned int suspended:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct notifier_block i2c_restart_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bool system_restarting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct rk_tb_client tb_cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sended);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void rk3x_i2c_wake_up(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!i2c->system_restarting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) wake_up(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(value, i2c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return readl(i2c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Reset all interrupt pending bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) i2c_writel(i2c, REG_INT_ALL, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static inline void rk3x_i2c_disable_irq(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) i2c_writel(i2c, IEN_ALL_DISABLE, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static inline void rk3x_i2c_disable(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) i2c_writel(i2c, val, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static bool rk3x_i2c_auto_stop(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int len, con1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!i2c->autostop_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) con1 = REG_CON1_NACK_AUTO_STOP | REG_CON1_AUTO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!i2c->is_last_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) len = i2c->msg->len - i2c->processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) i2c->state = STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) con1 |= REG_CON1_TRANSFER_AUTO_STOP | REG_CON1_AUTO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) i2c_writel(i2c, con1, REG_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (con1 & REG_CON1_NACK_AUTO_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) i2c_writel(i2c, REG_INT_STOP, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) i2c_writel(i2c, REG_INT_STOP | REG_INT_NAKRCV, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) i2c_writel(i2c, con1, REG_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Generate a START condition, which triggers a REG_INT_START interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void rk3x_i2c_start(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool auto_stop = rk3x_i2c_auto_stop(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* enable appropriate interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (i2c->mode == REG_CON_MOD_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!auto_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) i2c->state = STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) length = rk3x_i2c_fill_transmit_buf(i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* in any other case, we are going to be reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!auto_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) i2c->state = STATE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* enable adapter with correct mode, send START condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* if we want to react to NACK, set ACTACK bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val |= REG_CON_ACTACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i2c_writel(i2c, val, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* enable transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (i2c->mode == REG_CON_MOD_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) i2c_writel(i2c, length, REG_MTXCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rk3x_i2c_prepare_read(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * @error: Error code to return in rk3x_i2c_xfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i2c->processed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) i2c->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) i2c->error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (i2c->is_last_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Enable stop interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) i2c_writel(i2c, REG_INT_STOP, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) i2c->state = STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ctrl = i2c_readl(i2c, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ctrl |= REG_CON_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctrl &= ~REG_CON_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) i2c_writel(i2c, ctrl, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Signal rk3x_i2c_xfer to start the next message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c->busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * The HW is actually not capable of REPEATED START. But we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * get the intended effect by resetting its internal state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * and issuing an ordinary START.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) i2c_writel(i2c, ctrl, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* signal that we are finished with the current msg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rk3x_i2c_wake_up(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Setup a read according to i2c->msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int len = i2c->msg->len - i2c->processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) con = i2c_readl(i2c, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * The hw can read up to 32 bytes at a time. If we need more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * chunk, send an ACK after the last byte of the current chunk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (len > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) con &= ~REG_CON_LASTACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) con |= REG_CON_LASTACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* make sure we are in plain RX mode if we read a second chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (i2c->processed != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) con &= ~REG_CON_MOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) con |= REG_CON_MOD(REG_CON_MOD_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (con & REG_CON_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) con &= ~REG_CON_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) i2c_writel(i2c, con, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) i2c_writel(i2c, len, REG_MRXCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Fill the transmit buffer with data from i2c->msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c, bool sendend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (i = 0; i < 8; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) for (j = 0; j < 4; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((i2c->processed == i2c->msg->len) && (cnt != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (i2c->processed == 0 && cnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) byte = (i2c->addr & 0x7f) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) byte = i2c->msg->buf[i2c->processed++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) val |= byte << (j * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (i2c->processed == i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (sendend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i2c_writel(i2c, cnt, REG_MTXCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* IRQ handlers for individual states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!(ipd & REG_INT_MBTF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rk3x_i2c_stop(i2c, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_warn_ratelimited(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rk3x_i2c_clean_ipd(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* ack interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rk3x_i2c_auto_stop(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* are we finished? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (i2c->processed == i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rk3x_i2c_stop(i2c, i2c->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rk3x_i2c_fill_transmit_buf(i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void rk3x_i2c_read(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int len = i2c->msg->len - i2c->processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Can only handle a maximum of 32 bytes at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) len = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* read the data from receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < len; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (i % 4 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) byte = (val >> ((i % 4) * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) i2c->msg->buf[i2c->processed++] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* we only care for MBRF here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!(ipd & REG_INT_MBRF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* ack interrupt (read also produces a spurious START flag, clear it too) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* read the data from receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rk3x_i2c_read(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) rk3x_i2c_auto_stop(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* are we finished? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (i2c->processed == i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rk3x_i2c_stop(i2c, i2c->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rk3x_i2c_prepare_read(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!(ipd & REG_INT_STOP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rk3x_i2c_stop(i2c, -EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_warn_ratelimited(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rk3x_i2c_clean_ipd(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (i2c->autostop_supported && !i2c->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (i2c->mode != REG_CON_MOD_TX && i2c->msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if ((i2c->msg->len - i2c->processed) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rk3x_i2c_read(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i2c->processed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) i2c->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* ack interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) i2c_writel(i2c, REG_INT_STOP, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* disable STOP bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) con = i2c_readl(i2c, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) con &= ~REG_CON_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (i2c->autostop_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) con &= ~REG_CON_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2c_writel(i2c, con, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) i2c->busy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* signal rk3x_i2c_xfer that we are finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) rk3x_i2c_wake_up(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct rk3x_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int ipd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) spin_lock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ipd = i2c_readl(i2c, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (i2c->state == STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_warn_ratelimited(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "irq in STATE_IDLE, ipd = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) rk3x_i2c_clean_ipd(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Clean interrupt bits we don't care about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ipd &= ~(REG_INT_BRF | REG_INT_BTF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ipd & REG_INT_NAKRCV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * We got a NACK in the last operation. Depending on whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * IGNORE_NAK is set, we have to stop the operation and report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ipd &= ~REG_INT_NAKRCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (i2c->autostop_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) i2c->error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) i2c->state = STATE_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) rk3x_i2c_stop(i2c, -ENXIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* is there anything left to handle? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if ((ipd & REG_INT_ALL) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) switch (i2c->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case STATE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rk3x_i2c_handle_write(i2c, ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case STATE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rk3x_i2c_handle_read(i2c, ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case STATE_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) rk3x_i2c_handle_stop(i2c, ipd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case STATE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) spin_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * Get timing values of I2C specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * @speed: Desired SCL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Returns: Matched i2c spec values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return &standard_mode_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else if (speed <= I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return &fast_mode_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return &fast_mode_plus_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Calculate divider values for desired SCL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @clk_rate: I2C input clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @t: Known I2C timing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * @t_calc: Caculated rk3x private timings that would be written into regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * a best-effort divider value is returned in divs. If the target rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * too high, we silently use the highest possible rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct i2c_timings *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct rk3x_i2c_calced_timings *t_calc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned long min_low_ns, min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned long max_low_ns, min_total_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned long clk_rate_khz, scl_rate_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned long min_low_div, min_high_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned long max_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned long min_div_for_hold, min_total_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned long extra_div, extra_low_div, ideal_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned long data_hold_buffer_ns = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) const struct i2c_spec_values *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Only support standard-mode and fast-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* prevent scl_rate_khz from becoming 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (WARN_ON(t->bus_freq_hz < 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) t->bus_freq_hz = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * min_low_ns: The minimum number of ns we need to hold low to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * meet I2C specification, should include fall time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * min_high_ns: The minimum number of ns we need to hold high to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * meet I2C specification, should include rise time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * max_low_ns: The maximum number of ns we can hold low to meet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * I2C specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * This is because the i2c host on Rockchip holds the data line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * for half the low time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) spec = rk3x_i2c_get_spec(t->bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) min_high_ns = t->scl_rise_ns + spec->min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Timings for repeated start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * - controller appears to drop SDA at .875x (7/8) programmed clk high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * - controller appears to keep SCL high for 2x programmed clk high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * We need to account for those rules in picking our "high" time so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * we meet tSU;STA and tHD;STA times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) min_high_ns = max(min_high_ns, DIV_ROUND_UP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) min_high_ns = max(min_high_ns, DIV_ROUND_UP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) spec->min_high_ns), 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) min_low_ns = t->scl_fall_ns + spec->min_low_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) min_total_ns = min_low_ns + min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Adjust to avoid overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) scl_rate_khz = t->bus_freq_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * We need the total div to be >= this number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * so we don't clock too fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* These are the min dividers needed for min hold times. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) min_div_for_hold = (min_low_div + min_high_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * This is the maximum divider so we don't go over the maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * We don't round up here (we round down) since this is a maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (min_low_div > max_low_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) WARN_ONCE(true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "Conflicting, min_low_div %lu, max_low_div %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) min_low_div, max_low_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) max_low_div = min_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (min_div_for_hold > min_total_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * Time needed to meet hold requirements is important.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Just use that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) t_calc->div_low = min_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) t_calc->div_high = min_high_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * We've got to distribute some time among the low and high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * so we don't run too fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) extra_div = min_total_div - min_div_for_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * We'll try to split things up perfectly evenly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * biasing slightly towards having a higher div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * for low (spend more time low).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) scl_rate_khz * 8 * min_total_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Don't allow it to go over the maximum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ideal_low_div > max_low_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ideal_low_div = max_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Handle when the ideal low div is going to take up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * more than we have.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ideal_low_div > min_low_div + extra_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ideal_low_div = min_low_div + extra_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Give low the "ideal" and give high whatever extra is left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) extra_low_div = ideal_low_div - min_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) t_calc->div_low = ideal_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) t_calc->div_high = min_high_div + (extra_div - extra_low_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * Adjust to the fact that the hardware has an implicit "+1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) t_calc->div_low--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) t_calc->div_high--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Give the tuning value 0, that would not update con register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) t_calc->tuning = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Maximum divider supported by hw is 0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (t_calc->div_low > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) t_calc->div_low = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (t_calc->div_high > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) t_calc->div_high = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Calculate timing values for desired SCL frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * @clk_rate: I2C input clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * @t: Known I2C timing information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * @t_calc: Caculated rk3x private timings that would be written into regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * a best-effort divider value is returned in divs. If the target rate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * too high, we silently use the highest possible rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * The following formulas are v1's method to calculate timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * l = divl + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * h = divh + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * s = sda_update_config + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * u = start_setup_config + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * p = stop_setup_config + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * T = Tclk_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * tHigh = 8 * h * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * tLow = 8 * l * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * tHD;sda = (l * s + 1) * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * tSU;sda = [(8 - s) * l + 1] * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * tI2C = 8 * (l + h) * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * tSU;sta = (8h * u + 1) * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * tHD;sta = [8h * (u + 1) - 1] * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * tSU;sto = (8h * p + 1) * T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct i2c_timings *t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct rk3x_i2c_calced_timings *t_calc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned long min_low_ns, min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned long min_setup_start_ns, min_setup_data_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned long min_setup_stop_ns, max_hold_data_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long clk_rate_khz, scl_rate_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned long min_low_div, min_high_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned long min_div_for_hold, min_total_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned long extra_div, extra_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) const struct i2c_spec_values *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Support standard-mode, fast-mode and fast-mode plus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* prevent scl_rate_khz from becoming 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (WARN_ON(t->bus_freq_hz < 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) t->bus_freq_hz = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * min_low_ns: The minimum number of ns we need to hold low to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * meet I2C specification, should include fall time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * min_high_ns: The minimum number of ns we need to hold high to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * meet I2C specification, should include rise time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) spec = rk3x_i2c_get_spec(t->bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* calculate min-divh and min-divl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) scl_rate_khz = t->bus_freq_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) min_high_ns = t->scl_rise_ns + spec->min_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) min_low_ns = t->scl_fall_ns + spec->min_low_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Final divh and divl must be greater than 0, otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * hardware would not output the i2c clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) min_high_div = (min_high_div < 1) ? 2 : min_high_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) min_low_div = (min_low_div < 1) ? 2 : min_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* These are the min dividers needed for min hold times. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) min_div_for_hold = (min_low_div + min_high_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * This is the maximum divider so we don't go over the maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * We don't round up here (we round down) since this is a maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (min_div_for_hold >= min_total_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Time needed to meet hold requirements is important.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * Just use that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) t_calc->div_low = min_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) t_calc->div_high = min_high_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * We've got to distribute some time among the low and high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * so we don't run too fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * We'll try to split things up by the scale of min_low_div and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * min_high_div, biasing slightly towards having a higher div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * for low (spend more time low).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) extra_div = min_total_div - min_div_for_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) min_div_for_hold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) t_calc->div_low = min_low_div + extra_low_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) t_calc->div_high = min_high_div + (extra_div - extra_low_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * calculate sda data hold count by the rules, data_upd_st:3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * is a appropriate value to reduce calculated times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * (t_calc->div_low) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * 1000000, clk_rate_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * (t_calc->div_low) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * 1000000, clk_rate_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if ((max_hold_data_ns < spec->max_data_hold_ns) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (min_setup_data_ns > spec->min_data_setup_ns))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* calculate setup start config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) - 1000000, 8 * 1000000 * (t_calc->div_high));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* calculate setup stop config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) - 1000000, 8 * 1000000 * (t_calc->div_high));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) REG_CON_STA_CFG(--stp_sta_cfg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) REG_CON_STO_CFG(--stp_sto_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) t_calc->div_low--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) t_calc->div_high--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Maximum divider supported by hw is 0xffff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (t_calc->div_low > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) t_calc->div_low = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (t_calc->div_high > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) t_calc->div_high = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct i2c_timings *t = &i2c->t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct rk3x_i2c_calced_timings calc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u64 t_low_ns, t_high_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) clk_enable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) val = i2c_readl(i2c, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) val &= ~REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) val |= calc.tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) i2c_writel(i2c, val, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) REG_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) clk_disable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) clk_rate / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) 1000000000 / t->bus_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) t_low_ns, t_high_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * rk3x_i2c_clk_notifier_cb - Clock rate change callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * @nb: Pointer to notifier block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * @event: Notification reason
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * @data: Pointer to notification data object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * The callback checks whether a valid bus frequency can be generated after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * change. If so, the change is acknowledged, otherwise the change is aborted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * New dividers are written to the HW in the pre- or post change notification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * depending on the scaling direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * Code adapted from i2c-cadence.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * to acknowledge the change, NOTIFY_DONE if the notification is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * considered irrelevant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct rk3x_i2c_calced_timings calc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Try the calculation (but don't store the result) ahead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * time to see if we need to block the clock change. Timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * shouldn't actually take effect until rk3x_i2c_adapt_div().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) &calc) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return NOTIFY_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* scale up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) rk3x_i2c_adapt_div(i2c, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* scale down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) rk3x_i2c_adapt_div(i2c, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* scale up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) rk3x_i2c_adapt_div(i2c, ndata->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * Setup I2C registers for an I2C operation specified by msgs, num.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * Must be called with i2c->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * @msgs: I2C msgs to process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * @num: Number of msgs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * returns: Number of I2C msgs processed or negative in case of error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u32 addr = (msgs[0].addr & 0x7f) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * The I2C adapter can issue a small (len < 4) write packet before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * reading. This speeds up SMBus-style register reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * The MRXADDR/MRXRADDR hold the slave address and the slave register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * address in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (num >= 2 && msgs[0].len < 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u32 reg_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) addr >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Fill MRXRADDR with the register address(es) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) for (i = 0; i < msgs[0].len; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) reg_addr |= msgs[0].buf[i] << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) reg_addr |= REG_MRXADDR_VALID(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* msgs[0] is handled by hw. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) i2c->msg = &msgs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) i2c->mode = REG_CON_MOD_REGISTER_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) i2c_writel(i2c, reg_addr, REG_MRXRADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * We'll have to do it the boring way and process the msgs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * one-by-one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (msgs[0].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) addr |= 1; /* set read bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * We have to transmit the slave addr first. Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * MOD_REGISTER_TX for that purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) i2c->mode = REG_CON_MOD_REGISTER_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) REG_MRXADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) i2c_writel(i2c, 0, REG_MRXRADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) i2c->mode = REG_CON_MOD_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) i2c->msg = &msgs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) i2c->addr = msgs[0].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) i2c->busy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) i2c->processed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) i2c->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) rk3x_i2c_clean_ipd(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (i2c->autostop_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) i2c_writel(i2c, 0, REG_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c, unsigned long xfer_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ktime_t timeout = ktime_add_ms(ktime_get(), xfer_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) while (READ_ONCE(i2c->busy) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ktime_compare(ktime_get(), timeout) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) rk3x_i2c_irq(0, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return !i2c->busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct i2c_msg *msgs, int num, bool polling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) unsigned long timeout, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (i2c->suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) clk_enable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) i2c->is_last_msg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * Process msgs. We can handle more than one message at once (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * rk3x_i2c_setup()).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) for (i = 0; i < num; i += ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned long xfer_time = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Transfer time in mSec = Total bits / transfer rate + interval time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) len = msgs[i + 1].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) len = msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) xfer_time += len / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) xfer_time += DIV_ROUND_CLOSEST(((len * 9) + 2) * MSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) i2c->t.bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (i + ret >= num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) i2c->is_last_msg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) rk3x_i2c_start(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (!polling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) timeout = wait_event_timeout(i2c->wait, !i2c->busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) msecs_to_jiffies(xfer_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) timeout = rk3x_i2c_wait_xfer_poll(i2c, xfer_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) i2c_readl(i2c, REG_IPD), i2c->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* Force a STOP condition without interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) rk3x_i2c_disable_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) val |= REG_CON_EN | REG_CON_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) i2c_writel(i2c, val, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (i2c->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = i2c->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) rk3x_i2c_disable_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) rk3x_i2c_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) clk_disable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return ret < 0 ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static int rk3x_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return rk3x_i2c_xfer_common(adap, msgs, num, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return rk3x_i2c_xfer_common(adap, msgs, num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int rk3x_i2c_restart_notify(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned long mode, void *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct rk3x_i2c *i2c = container_of(this, struct rk3x_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) i2c_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) int tmo = WAIT_TIMEOUT * USEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (i2c->state != STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) i2c->system_restarting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* complete the unfinished job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) while (tmo-- && i2c->busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) rk3x_i2c_irq(0, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (tmo <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_err(i2c->dev, "restart timeout, ipd: 0x%02x, state: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) i2c_readl(i2c, REG_IPD), i2c->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Force a STOP condition without interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) i2c_writel(i2c, 0, REG_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val |= REG_CON_EN | REG_CON_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) i2c_writel(i2c, val, REG_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static unsigned int rk3x_i2c_get_version(struct rk3x_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) clk_enable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) version = i2c_readl(i2c, REG_CON) & REG_CON_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) clk_disable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) version >>= REG_CON_VERSION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int rk3x_i2c_of_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int bus_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (IS_ENABLED(CONFIG_OF) && dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) bus_id = of_alias_get_id(dev->of_node, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int rk3x_i2c_acpi_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) unsigned long bus_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) const char *uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) uid = acpi_device_uid(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!uid || !(*uid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_err(dev, "Cannot retrieve UID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = kstrtoul(uid, 0, &bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return !ret ? bus_id : -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int rk3x_i2c_acpi_get_bus_id(struct device *dev, struct rk3x_i2c *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static __maybe_unused int rk3x_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct rk3x_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * Below code is needed only to ensure that there are no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * activities on I2C bus. if at this moment any driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * is trying to use I2C bus - this may cause i2c timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * So forbid access to I2C device using i2c->suspended flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) i2c->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static __maybe_unused int rk3x_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) struct rk3x_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Allow access to I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) i2c->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static u32 rk3x_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const struct i2c_algorithm rk3x_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .master_xfer = rk3x_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .master_xfer_atomic = rk3x_i2c_xfer_polling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .functionality = rk3x_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static const struct rk3x_i2c_soc_data rv1108_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .grf_offset = 0x408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .calc_timings = rk3x_i2c_v1_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const struct rk3x_i2c_soc_data rv1126_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .grf_offset = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .calc_timings = rk3x_i2c_v1_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const struct rk3x_i2c_soc_data rk3066_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .grf_offset = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .calc_timings = rk3x_i2c_v0_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static const struct rk3x_i2c_soc_data rk3188_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .grf_offset = 0x0a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .calc_timings = rk3x_i2c_v0_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static const struct rk3x_i2c_soc_data rk3228_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .grf_offset = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .calc_timings = rk3x_i2c_v0_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const struct rk3x_i2c_soc_data rk3288_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .grf_offset = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .calc_timings = rk3x_i2c_v0_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const struct rk3x_i2c_soc_data rk3399_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .grf_offset = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .calc_timings = rk3x_i2c_v1_calc_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const struct of_device_id rk3x_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .compatible = "rockchip,rv1108-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .data = &rv1108_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .compatible = "rockchip,rv1126-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .data = &rv1126_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .compatible = "rockchip,rk3066-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .data = &rk3066_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .compatible = "rockchip,rk3188-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .data = &rk3188_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .compatible = "rockchip,rk3228-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .data = &rk3228_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .compatible = "rockchip,rk3288-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .data = &rk3288_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .compatible = "rockchip,rk3399-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .data = &rk3399_soc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static void rk3x_i2c_tb_cb(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) unsigned int irq = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static int rk3x_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct fwnode_handle *fw = dev_fwnode(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct rk3x_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) i2c->soc_data = (struct rk3x_i2c_soc_data *)device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = rk3x_i2c_acpi_get_bus_id(&pdev->dev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = rk3x_i2c_of_get_bus_id(&pdev->dev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) i2c->adap.nr = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* use common interface to get I2C timing properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) i2c->adap.algo = &rk3x_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) i2c->adap.retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) i2c->adap.algo_data = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) i2c->adap.dev.fwnode = fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) spin_lock_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) init_waitqueue_head(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) i2c->i2c_restart_nb.notifier_call = rk3x_i2c_restart_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) i2c->i2c_restart_nb.priority = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ret = register_pre_restart_handler(&i2c->i2c_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev_err(&pdev->dev, "failed to setup i2c restart handler.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) i2c->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (IS_ERR(i2c->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return PTR_ERR(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * Switch to new interface if the SoC also offers the old one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * The control bit is located in the GRF register space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (i2c->soc_data->grf_offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (!IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) int bus_nr = i2c->adap.nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (i2c->soc_data == &rv1108_soc_data && bus_nr == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* rv1108 i2c2 set grf offset-0x408, bit-10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) value = BIT(26) | BIT(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) else if (i2c->soc_data == &rv1126_soc_data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) bus_nr == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* rv1126 i2c2 set pmugrf offset-0x118, bit-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) value = BIT(20) | BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* rk3xxx 27+i: write mask, 11+i: value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = regmap_write(grf, i2c->soc_data->grf_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_err(i2c->dev, "Could not write to GRF: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* IRQ setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) device_property_read_bool(&pdev->dev, "rockchip,amp-shared")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) i2c->tb_cl.data = (void *)(unsigned long)irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) i2c->tb_cl.cb = rk3x_i2c_tb_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) irq_set_status_flags(irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) 0, dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev_err(&pdev->dev, "cannot request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE) && i2c->tb_cl.cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) rk_tb_client_register_cb(&i2c->tb_cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (!has_acpi_companion(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* Only one clock to use for bus clock and peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) i2c->pclk = i2c->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) i2c->clk = devm_clk_get(&pdev->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (IS_ERR(i2c->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) "Can't get bus clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (IS_ERR(i2c->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) "Can't get periph clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = clk_prepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ret = clk_prepare(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (i2c->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) dev_err(&pdev->dev, "Unable to register clock notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) goto err_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) clk_rate = clk_get_rate(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) device_property_read_u32(&pdev->dev, "i2c,clk-rate", (u32 *)&clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) rk3x_i2c_adapt_div(i2c, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (rk3x_i2c_get_version(i2c) >= RK_I2C_VERSION5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) i2c->autostop_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ret = i2c_add_numbered_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) goto err_clk_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) err_clk_notifier:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) err_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) clk_unprepare(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static int rk3x_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) unregister_pre_restart_handler(&i2c->i2c_restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) clk_unprepare(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static const struct dev_pm_ops rk3x_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rk3x_i2c_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) rk3x_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static struct platform_driver rk3x_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .probe = rk3x_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .remove = rk3x_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .name = "rk3x-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .of_match_table = rk3x_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .pm = &rk3x_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static int __init rk3x_i2c_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return platform_driver_register(&rk3x_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #ifdef CONFIG_INITCALL_ASYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) subsys_initcall_sync(rk3x_i2c_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) subsys_initcall(rk3x_i2c_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static void __exit rk3x_i2c_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) platform_driver_unregister(&rk3x_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) module_exit(rk3x_i2c_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) module_platform_driver(rk3x_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags