^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Renesas R-Car I2C unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2019 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2012-14 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is based on the drivers/i2c/busses/i2c-sh7760.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/i2c-smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ICSCR 0x00 /* slave ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ICMCR 0x04 /* master ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ICSSR 0x08 /* slave status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ICMSR 0x0C /* master status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ICSIER 0x10 /* slave irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ICMIER 0x14 /* master irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ICCCR 0x18 /* clock dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ICSAR 0x1C /* slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ICMAR 0x20 /* master address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ICRXTX 0x24 /* data port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ICDMAER 0x3c /* DMA enable (Gen3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* ICSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDBS (1 << 3) /* slave data buffer select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIE (1 << 2) /* slave interface enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCAE (1 << 1) /* general call address enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FNA (1 << 0) /* forced non acknowledgment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* ICMCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MDBS (1 << 7) /* non-fifo mode switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSCL (1 << 6) /* override SCL pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FSDA (1 << 5) /* override SDA pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OBPC (1 << 4) /* override pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MIE (1 << 3) /* master if enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TSBE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FSB (1 << 1) /* force stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ESG (1 << 0) /* enable start bit gen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ICSSR (also for ICSIER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCAR (1 << 6) /* general call received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM (1 << 5) /* slave transmit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SSR (1 << 4) /* stop received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDE (1 << 3) /* slave data empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDT (1 << 2) /* slave data transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDR (1 << 1) /* slave data received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAR (1 << 0) /* slave addr received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ICMSR (also for ICMIE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MNR (1 << 6) /* nack received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAL (1 << 5) /* arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MST (1 << 4) /* sent a stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MDE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MDT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MDR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAT (1 << 0) /* slave addr xfer done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* ICDMAER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RMDMAE (1 << 1) /* DMA Master Received Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* ICFBSCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RCAR_MIN_DMA_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RCAR_IRQ_STOP (MST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ID_LAST_MSG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ID_FIRST_MSG (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ID_DONE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ID_ARBLOST (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ID_NACK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* persistent flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ID_P_HOST_NOTIFY BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ID_P_REP_AFTER_RD BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ID_P_PM_BLOCKED BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ID_P_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum rcar_i2c_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) I2C_RCAR_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) I2C_RCAR_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) I2C_RCAR_GEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct rcar_i2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int msgs_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 icccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 recovery_icmcr; /* protected by adapter lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) enum rcar_i2c_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct scatterlist sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum dma_data_direction dma_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_client *host_notify_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(val, priv->io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return readl(priv->io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int rcar_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->recovery_icmcr |= FSCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) priv->recovery_icmcr &= ~FSCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) priv->recovery_icmcr |= FSDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) priv->recovery_icmcr &= ~FSDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return !(rcar_i2c_read(priv, ICMCR) & FSDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct i2c_bus_recovery_info rcar_i2c_bri = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .get_scl = rcar_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .set_scl = rcar_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .set_sda = rcar_i2c_set_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .get_bus_free = rcar_i2c_get_bus_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void rcar_i2c_init(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* reset master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rcar_i2c_write(priv, ICMIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rcar_i2c_write(priv, ICMCR, MDBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rcar_i2c_write(priv, ICMSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* start clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rcar_i2c_write(priv, ICCCR, priv->icccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (priv->devtype == I2C_RCAR_GEN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rcar_i2c_write(priv, ICFBSCR, TCYC17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Waiting did not help, try to recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = i2c_recover_bus(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 scgd, cdf, round, ick, sum, scl, cdf_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct device *dev = rcar_i2c_priv_to_dev(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i2c_timings t = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .scl_fall_ns = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .scl_rise_ns = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .scl_int_delay_ns = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Fall back to previously used values if not supplied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) i2c_parse_fw_timings(dev, &t, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) switch (priv->devtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case I2C_RCAR_GEN1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cdf_width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case I2C_RCAR_GEN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case I2C_RCAR_GEN3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cdf_width = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(dev, "device type error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * calculate SCL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * ICCCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * ick = clkp / (1 + CDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * ick : I2C internal clock < 20 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * ticf : I2C SCL falling time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * tr : I2C SCL rising time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * intd : LSI internal delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * clkp : peripheral_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * F[] : integer up-valuation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cdf = rate / 20000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (cdf >= 1U << cdf_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(dev, "Input clock %lu too high\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ick = rate / (cdf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * it is impossible to calculate large scale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * number on u32. separate it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * = F[sum * ick / 1000000000]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * = F[(ick / 1000000) * sum / 1000]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) round = (ick + 500000) / 1000000 * sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) round = (round + 500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Calculation result (= SCL) should be less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * bus_speed for hardware safety
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * We could use something along the lines of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * div = ick / (bus_speed + 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * scgd = (div - 20 - round + 7) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * scl = ick / (20 + (scgd * 8) + round);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * (not fully verified) but that would get pretty involved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (scgd = 0; scgd < 0x40; scgd++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) scl = ick / (20 + (scgd * 8) + round);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (scl <= t.bus_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto scgd_find;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(dev, "it is impossible to calculate best SCL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) scgd_find:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) scl, t.bus_freq_hz, rate, round, cdf, scgd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* keep icccr value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv->icccr = scgd << cdf_width | cdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int read = !!rcar_i2c_is_recv(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) priv->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (priv->msgs_left == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) priv->flags |= ID_LAST_MSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * We don't have a test case but the HW engineers say that the write order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * it didn't cause a drawback for me, let's rather be safe than sorry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (priv->flags & ID_FIRST_MSG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rcar_i2c_write(priv, ICMSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (priv->flags & ID_P_REP_AFTER_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) priv->flags &= ~ID_P_REP_AFTER_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) rcar_i2c_write(priv, ICMSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) priv->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->msgs_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->flags &= ID_P_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rcar_i2c_prepare_msg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ? priv->dma_rx : priv->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) sg_dma_len(&priv->sg), priv->dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Gen3 can only do one RXDMA per transfer and we just completed it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (priv->devtype == I2C_RCAR_GEN3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) priv->dma_direction == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->flags |= ID_P_NO_RXDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->dma_direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Disable DMA Master Received/Transmitted, must be last! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) rcar_i2c_write(priv, ICDMAER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (priv->dma_direction == DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) else if (priv->dma_direction == DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dmaengine_terminate_all(priv->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) else if (priv->dma_direction == DMA_TO_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dmaengine_terminate_all(priv->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) rcar_i2c_dma_unmap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void rcar_i2c_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct rcar_i2c_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) priv->pos += sg_dma_len(&priv->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) rcar_i2c_dma_unmap(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct device *dev = rcar_i2c_priv_to_dev(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool read = msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Do various checks to see if DMA is feasible at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * The last two bytes needs to be fetched using PIO in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * order for the STOP phase to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) buf = priv->msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) len = priv->msg->len - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * First byte in message was sent using PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) buf = priv->msg->buf + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) len = priv->msg->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (dma_mapping_error(chan->device->dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_dbg(dev, "dma map failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sg_dma_len(&priv->sg) = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) sg_dma_address(&priv->sg) = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) priv->dma_direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!txdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rcar_i2c_cleanup_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) txdesc->callback = rcar_i2c_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) txdesc->callback_param = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cookie = dmaengine_submit(txdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (dma_submit_error(cookie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_dbg(dev, "submitting dma failed, using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rcar_i2c_cleanup_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Enable DMA Master Received/Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rcar_i2c_write(priv, ICDMAER, RMDMAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rcar_i2c_write(priv, ICDMAER, TMDMAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* FIXME: sometimes, unknown interrupt happened. Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!(msr & MDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Check if DMA can be enabled and take over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (priv->pos == 1 && rcar_i2c_dma(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (priv->pos < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Prepare next data to ICRXTX register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * This data will go to _SHIFT_ register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * [ICRXTX] -> [SHIFT] -> [I2C bus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) priv->pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * The last data was pushed to ICRXTX on _PREV_ empty irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * It is on _SHIFT_ register, and will sent to I2C bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * [ICRXTX] -> [SHIFT] -> [I2C bus]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (priv->flags & ID_LAST_MSG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * If current msg is the _LAST_ msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * prepare stop condition here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * ID_DONE will be set on STOP irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) rcar_i2c_next_msg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* FIXME: sometimes, unknown interrupt happened. Do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!(msr & MDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (msr & MAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Address transfer phase finished, but no data at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Try to use DMA to receive data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) rcar_i2c_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else if (priv->pos < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* get received data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) priv->pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* If next received data is the _LAST_, go to new phase. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (priv->pos + 1 == msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (priv->flags & ID_LAST_MSG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) priv->flags |= ID_P_REP_AFTER_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) rcar_i2c_next_msg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 ssr_raw, ssr_filtered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!ssr_filtered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* address detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ssr_filtered & SAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* read or write request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ssr_raw & STM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) rcar_i2c_write(priv, ICRXTX, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) rcar_i2c_read(priv, ICRXTX); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Clear SSR, too, because of old STOPs to other clients than us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* master sent stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ssr_filtered & SSR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rcar_i2c_write(priv, ICSIER, SAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* master wants to write to us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ssr_filtered & SDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) value = rcar_i2c_read(priv, ICRXTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Send NACK in case of error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* master wants to read from us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ssr_filtered & SDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rcar_i2c_write(priv, ICRXTX, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * This driver has a lock-free design because there are IP cores (at least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * R-Car Gen2) which have an inherent race condition in their hardware design.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * the interrupt was generated, otherwise an unwanted repeated message gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * generated. It turned out that taking a spinlock at the beginning of the ISR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * was already causing repeated messages. Thus, this driver was converted to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * the now lockless behaviour. Please keep this in mind when hacking the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * likely affected. Therefore, we have different interrupt handler entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (rcar_i2c_slave_irq(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (msr & MAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) priv->flags |= ID_DONE | ID_ARBLOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Nack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (msr & MNR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* HW automatically sends STOP after received NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) priv->flags |= ID_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (msr & MST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) priv->msgs_left--; /* The last message also made it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) priv->flags |= ID_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (rcar_i2c_is_recv(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) rcar_i2c_irq_recv(priv, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) rcar_i2c_irq_send(priv, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (priv->flags & ID_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) rcar_i2c_write(priv, ICMIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rcar_i2c_write(priv, ICMSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) wake_up(&priv->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct rcar_i2c_priv *priv = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Clear START or STOP immediately, except for REPSTART after read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (likely(!(priv->flags & ID_P_REP_AFTER_RD)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Only handle interrupts that are currently enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msr = rcar_i2c_read(priv, ICMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msr &= rcar_i2c_read(priv, ICMIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return rcar_i2c_irq(irq, priv, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct rcar_i2c_priv *priv = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Only handle interrupts that are currently enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) msr = rcar_i2c_read(priv, ICMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) msr &= rcar_i2c_read(priv, ICMIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Clear START or STOP immediately, except for REPSTART after read or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * if a spurious interrupt was detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (likely(!(priv->flags & ID_P_REP_AFTER_RD) && msr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return rcar_i2c_irq(irq, priv, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dma_addr_t port_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) chan = dma_request_chan(dev, chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_dbg(dev, "request_channel failed for %s (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) chan_name, PTR_ERR(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cfg.direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cfg.dst_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cfg.src_addr = port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_dbg(dev, "slave_config failed for %s (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) chan_name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dma_release_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(dev, "got DMA channel for %s\n", chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct device *dev = rcar_i2c_priv_to_dev(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) bool read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) read = msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) chan = read ? priv->dma_rx : priv->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (PTR_ERR(chan) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) priv->dma_rx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) priv->dma_tx = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!IS_ERR(priv->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dma_release_channel(priv->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!IS_ERR(priv->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dma_release_channel(priv->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* I2C is a special case, we need to poll the status of a reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = reset_control_reset(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 100, false, priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct device *dev = rcar_i2c_priv_to_dev(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /* Check bus state before init otherwise bus busy info will be lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = rcar_i2c_bus_barrier(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Gen3 needs a reset before allowing RXDMA once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (priv->devtype == I2C_RCAR_GEN3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) priv->flags |= ID_P_NO_RXDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!IS_ERR(priv->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = rcar_i2c_do_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) priv->flags &= ~ID_P_NO_RXDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rcar_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) rcar_i2c_request_dma(priv, msgs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* init first message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) priv->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) priv->msgs_left = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rcar_i2c_prepare_msg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) num * adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* cleanup DMA if it couldn't complete properly due to an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (priv->dma_direction != DMA_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rcar_i2c_cleanup_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) rcar_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } else if (priv->flags & ID_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } else if (priv->flags & ID_ARBLOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = num - priv->msgs_left; /* The number of transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret < 0 && ret != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(dev, "error %d : %x\n", ret, priv->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int rcar_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (priv->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Keep device active for slave address detection logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) priv->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) rcar_i2c_write(priv, ICSAR, slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rcar_i2c_write(priv, ICSSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rcar_i2c_write(priv, ICSIER, SAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) rcar_i2c_write(priv, ICSCR, SIE | SDBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int rcar_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) WARN_ON(!priv->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* ensure no irq is running before clearing ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) disable_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) rcar_i2c_write(priv, ICSIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) rcar_i2c_write(priv, ICSSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) enable_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) rcar_i2c_write(priv, ICSCR, SDBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) priv->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pm_runtime_put(rcar_i2c_priv_to_dev(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static u32 rcar_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * This HW can't do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * I2C_SMBUS_QUICK (setting FSB during START didn't work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * I2C_M_NOSTART (automatically sends address after START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (priv->flags & ID_P_HOST_NOTIFY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const struct i2c_algorithm rcar_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .master_xfer = rcar_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .functionality = rcar_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .reg_slave = rcar_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .unreg_slave = rcar_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct i2c_adapter_quirks rcar_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct of_device_id rcar_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int rcar_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct rcar_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned long irqflags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Otherwise logic will break because some bytes must always use PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev_err(dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (IS_ERR(priv->io))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return PTR_ERR(priv->io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) init_waitqueue_head(&priv->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) adap = &priv->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) adap->algo = &rcar_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) adap->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) adap->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) adap->bus_recovery_info = &rcar_i2c_bri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) adap->quirks = &rcar_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) i2c_set_adapdata(adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) strlcpy(adap->name, pdev->name, sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Init DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sg_init_table(&priv->sg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) priv->dma_direction = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Activate device for clock calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = rcar_i2c_clock_calculate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto out_pm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (priv->devtype < I2C_RCAR_GEN3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) irqflags |= IRQF_NO_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) irqhandler = rcar_i2c_gen2_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (priv->devtype == I2C_RCAR_GEN3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!IS_ERR(priv->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = reset_control_status(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) priv->rstc = ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Stay always active when multi-master to keep arbitration working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (of_property_read_bool(dev->of_node, "multi-master"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) priv->flags |= ID_P_PM_BLOCKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (of_property_read_bool(dev->of_node, "smbus"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) priv->flags |= ID_P_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto out_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) priv->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_err(dev, "cannot get irq %d\n", priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto out_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) goto out_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (priv->flags & ID_P_HOST_NOTIFY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (IS_ERR(priv->host_notify_client)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = PTR_ERR(priv->host_notify_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto out_del_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_info(dev, "probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) out_del_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) out_pm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) out_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int rcar_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (priv->host_notify_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) i2c_free_slave_host_notify_device(priv->host_notify_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) rcar_i2c_release_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (priv->flags & ID_P_PM_BLOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int rcar_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) i2c_mark_adapter_suspended(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static int rcar_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) i2c_mark_adapter_resumed(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const struct dev_pm_ops rcar_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define DEV_PM_OPS (&rcar_i2c_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static struct platform_driver rcar_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .name = "i2c-rcar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .of_match_table = rcar_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .pm = DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .probe = rcar_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .remove = rcar_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) module_platform_driver(rcar_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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