^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/qcom-geni-se.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SE_I2C_TX_TRANS_LEN 0x26c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SE_I2C_RX_TRANS_LEN 0x270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SE_I2C_SCL_COUNTERS 0x278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SE_I2C_ABORT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* M_CMD OP codes for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_WRITE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_READ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_WRITE_READ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_ADDR_ONLY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_BUS_CLEAR 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_STOP_ON_BUS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* M_CMD params for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PRE_CMD_DELAY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIMESTAMP_BEFORE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STOP_STRETCH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIMESTAMP_AFTER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define POST_COMMAND_DELAY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IGNORE_ADD_NACK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define READ_FINISHED_WITH_ACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BYPASS_ADDR_PHASE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLV_ADDR_MSK GENMASK(15, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLV_ADDR_SHFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* I2C SCL COUNTER fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HIGH_COUNTER_MSK GENMASK(29, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HIGH_COUNTER_SHFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LOW_COUNTER_MSK GENMASK(19, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LOW_COUNTER_SHFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CYCLE_COUNTER_MSK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum geni_i2c_err_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GP_IRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GP_IRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) BUS_PROTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ARB_LOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) GP_IRQ5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GENI_OVERRUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GENI_ILLEGAL_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GENI_ABORT_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GENI_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2C_AUTO_SUSPEND_DELAY 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KHZ(freq) (1000 * freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PACKING_BYTES_PW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ABORT_TIMEOUT HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XFER_TIMEOUT HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RST_TIMEOUT HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct geni_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct geni_se se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 tx_wm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct i2c_msg *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int cur_wr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int cur_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 clk_freq_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct geni_i2c_clk_fld *clk_fld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) size_t xfer_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct geni_i2c_err_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct geni_i2c_err_log gi2c_log[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct geni_i2c_clk_fld {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 clk_freq_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 t_high_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 t_low_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 t_cycle_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Hardware uses the underlying formula to calculate time periods of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * SCL clock cycle. Firmware uses some additional cycles excluded from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * below formula and it is confirmed that the time periods are within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * specification limits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * clk_freq_out = t / t_cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * source_clock = 19.2 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {KHZ(100), 7, 10, 11, 26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {KHZ(400), 2, 5, 12, 24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {KHZ(1000), 1, 3, 9, 18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (itr->clk_freq_out == gi2c->clk_freq_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) gi2c->clk_fld = itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= itr->t_cycle_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 rx_st, tx_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dma, tx_st, rx_st, m_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) m_cmd, geni_s, geni_ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!gi2c->err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) gi2c->err = gi2c_log[err].err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (gi2c->cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (err != NACK && err != GENI_ABORT_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) geni_i2c_err_misc(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static irqreturn_t geni_i2c_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct geni_i2c_dev *gi2c = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __iomem *base = gi2c->se.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int j, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 m_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 rx_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 dm_tx_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 dm_rx_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct i2c_msg *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock(&gi2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cur = gi2c->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!cur ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dm_rx_st & (DM_I2C_CB_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (m_stat & M_GP_IRQ_1_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) geni_i2c_err(gi2c, NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (m_stat & M_GP_IRQ_3_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) geni_i2c_err(gi2c, BUS_PROTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (m_stat & M_GP_IRQ_4_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) geni_i2c_err(gi2c, ARB_LOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (m_stat & M_CMD_OVERRUN_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) geni_i2c_err(gi2c, GENI_OVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (m_stat & M_ILLEGAL_CMD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (m_stat & M_CMD_ABORT_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) geni_i2c_err(gi2c, GENI_ABORT_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (m_stat & M_GP_IRQ_0_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) geni_i2c_err(gi2c, GP_IRQ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Disable the TX Watermark interrupt to stop TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else if (dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dm_tx_st, dm_rx_st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else if (cur->flags & I2C_M_RD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (j = 0; j < rxcnt; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) val = readl_relaxed(base + SE_GENI_RX_FIFOn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cur->buf[gi2c->cur_rd++] = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (gi2c->cur_rd == cur->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } else if (!(cur->flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) m_stat & M_TX_FIFO_WATERMARK_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (j = 0; j < gi2c->tx_wm; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) temp = cur->buf[gi2c->cur_wr++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val |= temp << (p * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel_relaxed(val, base + SE_GENI_TX_FIFOn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* TX Complete, Disable the TX Watermark interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (gi2c->cur_wr == cur->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (m_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (dma && dm_tx_st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (dma && dm_rx_st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* if this is err with done-bit not set, handle that through timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) complete(&gi2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_unlock(&gi2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long time_left = ABORT_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) spin_lock_irqsave(&gi2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) geni_i2c_err(gi2c, GENI_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gi2c->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) geni_se_abort_m_cmd(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock_irqrestore(&gi2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) time_left = wait_for_completion_timeout(&gi2c->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } while (!(val & M_CMD_ABORT_EN) && time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!(val & M_CMD_ABORT_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long time_left = RST_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) time_left = wait_for_completion_timeout(&gi2c->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } while (!(val & RX_RESET_DONE) && time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!(val & RX_RESET_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long time_left = RST_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) time_left = wait_for_completion_timeout(&gi2c->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) } while (!(val & TX_RESET_DONE) && time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!(val & TX_RESET_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct i2c_msg *cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gi2c->cur_rd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (gi2c->dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (gi2c->err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) geni_i2c_rx_fsm_rst(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct i2c_msg *cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) gi2c->cur_wr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (gi2c->dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (gi2c->err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) geni_i2c_tx_fsm_rst(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 m_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dma_addr_t rx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void *dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct geni_se *se = &gi2c->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) size_t len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct i2c_msg *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!of_machine_is_compatible("lenovo,yoga-c630"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) geni_se_select_mode(se, GENI_SE_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) geni_se_select_mode(se, GENI_SE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) geni_se_setup_m_cmd(se, I2C_READ, m_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) geni_se_select_mode(se, GENI_SE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gi2c->xfer_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) gi2c->dma_addr = rx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gi2c->dma_buf = dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) cur = gi2c->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) geni_i2c_abort_xfer(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) geni_i2c_rx_msg_cleanup(gi2c, cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return gi2c->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 m_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dma_addr_t tx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) void *dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct geni_se *se = &gi2c->se;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) size_t len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct i2c_msg *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!of_machine_is_compatible("lenovo,yoga-c630"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (dma_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) geni_se_select_mode(se, GENI_SE_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) geni_se_select_mode(se, GENI_SE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) geni_se_select_mode(se, GENI_SE_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gi2c->xfer_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) gi2c->dma_addr = tx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) gi2c->dma_buf = dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!dma_buf) /* Get FIFO IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cur = gi2c->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) geni_i2c_abort_xfer(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) geni_i2c_tx_msg_cleanup(gi2c, cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return gi2c->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int geni_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gi2c->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) reinit_completion(&gi2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = pm_runtime_get_sync(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pm_runtime_put_noidle(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Set device in suspended since resume failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pm_runtime_set_suspended(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) qcom_geni_i2c_conf(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gi2c->cur = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (msgs[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pm_runtime_mark_last_busy(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pm_runtime_put_autosuspend(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) gi2c->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gi2c->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static u32 geni_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct i2c_algorithm geni_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .master_xfer = geni_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .functionality = geni_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct acpi_device_id geni_i2c_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { "QCOM0220"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int geni_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct geni_i2c_dev *gi2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 proto, tx_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!gi2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gi2c->se.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gi2c->se.wrapper = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) gi2c->se.base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (IS_ERR(gi2c->se.base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return PTR_ERR(gi2c->se.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) gi2c->se.clk = devm_clk_get(dev, "se");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return PTR_ERR(gi2c->se.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = device_property_read_u32(dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &gi2c->clk_freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) gi2c->clk_freq_out = KHZ(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (has_acpi_companion(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) gi2c->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (gi2c->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return gi2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ret = geni_i2c_clk_map_idx(gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) gi2c->clk_freq_out, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) gi2c->adap.algo = &geni_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) init_completion(&gi2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spin_lock_init(&gi2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) platform_set_drvdata(pdev, gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_name(dev), gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(dev, "Request_irq failed:%d: err:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) gi2c->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Disable the interrupt so that the system can enter low-power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) disable_irq(gi2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) i2c_set_adapdata(&gi2c->adap, gi2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) gi2c->adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) gi2c->adap.dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = geni_icc_get(&gi2c->se, "qup-memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Set the bus quota for core and cpu to a reasonable value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Set quota for DDR based on bus speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = geni_icc_set_bw(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ret = geni_se_resources_on(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_err(dev, "Error turning on resources %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) proto = geni_se_read_proto(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (proto != GENI_SE_I2C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "Invalid proto %d\n", proto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) geni_se_resources_off(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) gi2c->tx_wm = tx_depth - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) true, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = geni_se_resources_off(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(dev, "Error turning off resources %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = geni_icc_disable(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) gi2c->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pm_runtime_set_suspended(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pm_runtime_use_autosuspend(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pm_runtime_enable(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = i2c_add_adapter(&gi2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(dev, "Error adding i2c adapter %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pm_runtime_disable(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int geni_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) i2c_del_adapter(&gi2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pm_runtime_disable(gi2c->se.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void geni_i2c_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Make client i2c transfers start failing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2c_mark_adapter_suspended(&gi2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) disable_irq(gi2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = geni_se_resources_off(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) enable_irq(gi2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) gi2c->suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return geni_icc_disable(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = geni_icc_enable(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = geni_se_resources_on(&gi2c->se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) enable_irq(gi2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) gi2c->suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) i2c_mark_adapter_suspended(&gi2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!gi2c->suspended) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) geni_i2c_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pm_runtime_set_suspended(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) i2c_mark_adapter_resumed(&gi2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct dev_pm_ops geni_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const struct of_device_id geni_i2c_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { .compatible = "qcom,geni-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct platform_driver geni_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .probe = geni_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .remove = geni_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .shutdown = geni_i2c_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .name = "geni_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .pm = &geni_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .of_match_table = geni_i2c_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) module_platform_driver(geni_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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