^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2017-20 Linaro Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CCI_HW_VERSION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CCI_RESET_CMD 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CCI_RESET_CMD_MASK 0x0f73f3f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CCI_RESET_CMD_M0_MASK 0x000003f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CCI_RESET_CMD_M1_MASK 0x0003f001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CCI_QUEUE_START 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CCI_HALT_REQ 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CCI_HALT_REQ_I2C_M0_Q0Q1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CCI_HALT_REQ_I2C_M1_Q0Q1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CCI_I2C_Mm_SCL_CTL(m) (0x100 + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CCI_I2C_Mm_SDA_CTL_0(m) (0x104 + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CCI_I2C_Mm_SDA_CTL_1(m) (0x108 + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CCI_I2C_Mm_SDA_CTL_2(m) (0x10c + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCI_I2C_Mm_MISC_CTL(m) (0x110 + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCI_I2C_Mm_READ_DATA(m) (0x118 + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCI_I2C_Mm_READ_BUF_LEVEL(m) (0x11c + 0x100 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n) (0x300 + 0x200 * (m) + 0x100 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n) (0x304 + 0x200 * (m) + 0x100 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCI_I2C_Mm_Qn_CUR_CMD(m, n) (0x308 + 0x200 * (m) + 0x100 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n) (0x30c + 0x200 * (m) + 0x100 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCI_I2C_Mm_Qn_LOAD_DATA(m, n) (0x310 + 0x200 * (m) + 0x100 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCI_IRQ_GLOBAL_CLEAR_CMD 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCI_IRQ_MASK_0 0xc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCI_IRQ_MASK_0_I2C_M0_RD_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCI_IRQ_MASK_0_I2C_M1_RD_DONE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCI_IRQ_MASK_0_RST_DONE_ACK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCI_IRQ_MASK_0_I2C_M0_ERROR 0x18000ee6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCI_IRQ_MASK_0_I2C_M1_ERROR 0x60ee6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCI_IRQ_CLEAR_0 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CCI_IRQ_STATUS_0 0xc0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CCI_IRQ_STATUS_0_I2C_M0_ERROR 0x18000ee6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CCI_IRQ_STATUS_0_I2C_M1_ERROR 0x60ee6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CCI_TIMEOUT (msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NUM_MASTERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NUM_QUEUES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Max number of resources + 1 for a NULL terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CCI_RES_MAX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CCI_I2C_SET_PARAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CCI_I2C_REPORT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CCI_I2C_WRITE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CCI_I2C_READ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CCI_I2C_REPORT_IRQ_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) I2C_MODE_STANDARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) I2C_MODE_FAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) I2C_MODE_FAST_PLUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum cci_i2c_queue_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) QUEUE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) QUEUE_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct hw_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 thigh; /* HIGH period of the SCL clock in clock ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 tlow; /* LOW period of the SCL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u16 tsu_sto; /* set-up time for STOP condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 tsu_sta; /* set-up time for a repeated START condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 thd_dat; /* data hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 thd_sta; /* hold time (repeated) START condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 tbuf; /* bus free time between a STOP and START condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 scl_stretch_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 trdhld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 tsp; /* pulse width of spikes suppressed by the input filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct cci_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct completion irq_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct cci *cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cci_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int num_masters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i2c_adapter_quirks quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 queue_size[NUM_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long cci_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct hw_params params[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct cci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct cci_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct clk_bulk_data *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int nclocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct cci_master master[NUM_MASTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static irqreturn_t cci_isr(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct cci *cci = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 val, reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val = readl(cci->base + CCI_IRQ_STATUS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(val, cci->base + CCI_IRQ_CLEAR_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) complete(&cci->master[0].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (cci->master[1].master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) complete(&cci->master[1].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cci->master[0].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) complete(&cci->master[0].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cci->master[1].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) complete(&cci->master[1].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reset = CCI_RESET_CMD_M0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reset = CCI_RESET_CMD_M1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (unlikely(reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writel(reset, cci->base + CCI_RESET_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cci->master[0].status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cci->master[0].status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cci->master[1].status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cci->master[1].status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int cci_halt(struct cci *cci, u8 master_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct cci_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (master_num >= cci->data->num_masters) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val = BIT(master_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) master = &cci->master[master_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reinit_completion(&master->irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(val, cci->base + CCI_HALT_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(cci->dev, "CCI halt timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int cci_reset(struct cci *cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * we reset the whole controller, here and for implicity use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * master[0].xxx for waiting on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) reinit_completion(&cci->master[0].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CCI_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(cci->dev, "CCI reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int cci_init(struct cci *cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CCI_IRQ_MASK_0_I2C_M1_RD_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CCI_IRQ_MASK_0_RST_DONE_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CCI_IRQ_MASK_0_I2C_M0_ERROR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CCI_IRQ_MASK_0_I2C_M1_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) writel(val, cci->base + CCI_IRQ_MASK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; i < cci->data->num_masters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int mode = cci->master[i].mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct hw_params *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!cci->master[i].cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) hw = &cci->data->params[mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = hw->thigh << 16 | hw->tlow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) val = hw->tsu_sto << 16 | hw->tsu_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val = hw->thd_dat << 16 | hw->thd_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = hw->tbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reinit_completion(&cci->master[master].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val = BIT(master * 2 + queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) writel(val, cci->base + CCI_QUEUE_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CCI_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(cci->dev, "master %d queue %d timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cci_reset(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cci_init(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return cci->master[master].status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (val == cci->data->queue_size[queue])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return cci_run_queue(cci, master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int cci_i2c_read(struct cci *cci, u16 master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u16 addr, u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 val, words_read, words_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 queue = QUEUE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int i, index = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Call validate queue to make sure queue is empty before starting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * This is to avoid overflow / underflow of queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = cci_validate_queue(cci, master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val = CCI_I2C_READ | len << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = cci_run_queue(cci, master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) words_exp = len / 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (words_read != words_exp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(cci->dev, "words read = %d, words expected = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) words_read, words_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < 4 && index < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* The LS byte of this register represents the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * first byte read from the slave during a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) first = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) buf[index++] = (val >> (i * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } while (--words_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int cci_i2c_write(struct cci *cci, u16 master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u16 addr, u8 *buf, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 queue = QUEUE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 load[12] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int i = 0, j, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Call validate queue to make sure queue is empty before starting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * This is to avoid overflow / underflow of queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = cci_validate_queue(cci, master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) load[i++] = CCI_I2C_WRITE | len << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) for (j = 0; j < len; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) load[i++] = buf[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (j = 0; j < i; j += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = load[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= load[j + 1] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val |= load[j + 2] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) val |= load[j + 3] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return cci_run_queue(cci, master, queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct cci_master *cci_master = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct cci *cci = cci_master->cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = pm_runtime_get_sync(cci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (msgs[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = cci_i2c_read(cci, cci_master->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msgs[i].addr, msgs[i].buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = cci_i2c_write(cci, cci_master->master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msgs[i].addr, msgs[i].buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pm_runtime_mark_last_busy(cci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pm_runtime_put_autosuspend(cci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static u32 cci_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct i2c_algorithm cci_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .master_xfer = cci_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .functionality = cci_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int cci_enable_clocks(struct cci *cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static void cci_disable_clocks(struct cci *cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int __maybe_unused cci_suspend_runtime(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct cci *cci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) cci_disable_clocks(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int __maybe_unused cci_resume_runtime(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct cci *cci = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = cci_enable_clocks(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cci_init(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int __maybe_unused cci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!pm_runtime_suspended(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return cci_suspend_runtime(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int __maybe_unused cci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cci_resume_runtime(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pm_request_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct dev_pm_ops qcom_cci_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int cci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned long cci_clk_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct cci *cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) platform_set_drvdata(pdev, cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cci->data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!cci->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for_each_available_child_of_node(dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = of_property_read_u32(child, "reg", &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_err(dev, "%pOF invalid 'reg' property", child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (idx >= cci->data->num_masters) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(dev, "%pOF invalid 'reg' value: %u (max is %u)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) child, idx, cci->data->num_masters - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cci->master[idx].adap.quirks = &cci->data->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) cci->master[idx].adap.algo = &cci_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) cci->master[idx].adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cci->master[idx].adap.dev.of_node = of_node_get(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cci->master[idx].master = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cci->master[idx].cci = cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) i2c_set_adapdata(&cci->master[idx].adap, &cci->master[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) snprintf(cci->master[idx].adap.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) sizeof(cci->master[idx].adap.name), "Qualcomm-CCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cci->master[idx].mode = I2C_MODE_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = of_property_read_u32(child, "clock-frequency", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (val == 400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cci->master[idx].mode = I2C_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else if (val == 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cci->master[idx].mode = I2C_MODE_FAST_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) init_completion(&cci->master[idx].irq_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cci->base = devm_ioremap_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(cci->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return PTR_ERR(cci->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = devm_clk_bulk_get_all(dev, &cci->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_err(dev, "failed to get clocks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cci->nclocks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Retrieve CCI clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (i = 0; i < cci->nclocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!strcmp(cci->clocks[i].id, "cci")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (cci_clk_rate != cci->data->cci_clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* cci clock set by the bootloader or via assigned clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * in DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cci_clk_rate, cci->data->cci_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = cci_enable_clocks(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cci->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = devm_request_irq(dev, cci->irq, cci_isr, 0, dev_name(dev), cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(dev, "request_irq failed, ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val = readl(cci->base + CCI_HW_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_dbg(dev, "CCI HW version = 0x%08x", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = cci_reset(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = cci_init(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (i = 0; i < cci->data->num_masters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!cci->master[i].cci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = i2c_add_adapter(&cci->master[i].adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) of_node_put(cci->master[i].adap.dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) error_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) for (--i ; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (cci->master[i].cci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2c_del_adapter(&cci->master[i].adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) of_node_put(cci->master[i].adap.dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) disable_irq(cci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) disable_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) cci_disable_clocks(cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int cci_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct cci *cci = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) for (i = 0; i < cci->data->num_masters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (cci->master[i].cci) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) i2c_del_adapter(&cci->master[i].adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) of_node_put(cci->master[i].adap.dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cci_halt(cci, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) disable_irq(cci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct cci_data cci_v1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .num_masters = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .queue_size = { 64, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .max_write_len = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .max_read_len = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .cci_clk_rate = 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .params[I2C_MODE_STANDARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .thigh = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .tlow = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .tsu_sto = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .tsu_sta = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .thd_dat = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .thd_sta = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .tbuf = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .scl_stretch_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .trdhld = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .tsp = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .params[I2C_MODE_FAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .thigh = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .tlow = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .tsu_sto = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .tsu_sta = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .thd_dat = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .thd_sta = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .tbuf = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .scl_stretch_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .trdhld = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .tsp = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct cci_data cci_v2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .num_masters = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .queue_size = { 64, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .max_write_len = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .max_read_len = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .cci_clk_rate = 37500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .params[I2C_MODE_STANDARD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .thigh = 201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .tlow = 174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .tsu_sto = 204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .tsu_sta = 231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .thd_dat = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .thd_sta = 162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .tbuf = 227,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .scl_stretch_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .trdhld = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .tsp = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .params[I2C_MODE_FAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .thigh = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .tlow = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .tsu_sto = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .tsu_sta = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .thd_dat = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .thd_sta = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .tbuf = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .scl_stretch_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .trdhld = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .tsp = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .params[I2C_MODE_FAST_PLUS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .thigh = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .tlow = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .tsu_sto = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .tsu_sta = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .thd_dat = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .thd_sta = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .tbuf = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .scl_stretch_en = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .trdhld = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .tsp = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct of_device_id cci_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) MODULE_DEVICE_TABLE(of, cci_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct platform_driver qcom_cci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .probe = cci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .remove = cci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .name = "i2c-qcom-cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .of_match_table = cci_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .pm = &qcom_cci_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) module_platform_driver(qcom_cci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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