^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Provides I2C support for Philips PNX010x/PNX4008 boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Vitaly Wool <vwool@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_PNX_SPEED_KHZ_DEFAULT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_PNX_REGION_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct i2c_pnx_mif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int ret; /* Return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int mode; /* Interface mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct completion complete; /* I/O completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct timer_list timer; /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 * buf; /* Data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int len; /* Length of data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int order; /* RX Bytes to order via TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_pnx_algo_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct i2c_pnx_mif mif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mstatus_tdi = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mstatus_afi = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mstatus_nai = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mstatus_drmi = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mstatus_active = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mstatus_scl = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mstatus_sda = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mstatus_rff = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mstatus_rfe = 0x00000200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mstatus_tff = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mstatus_tfe = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mcntrl_tdie = 0x00000001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mcntrl_afie = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mcntrl_naie = 0x00000004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mcntrl_drmie = 0x00000008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mcntrl_drsie = 0x00000010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mcntrl_rffie = 0x00000020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mcntrl_daie = 0x00000040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mcntrl_tffie = 0x00000080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mcntrl_reset = 0x00000100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mcntrl_cdbmode = 0x00000400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rw_bit = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) start_bit = 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) stop_bit = 1 << 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline int wait_timeout(struct i2c_pnx_algo_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) long timeout = data->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) while (timeout > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return (timeout <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline int wait_reset(struct i2c_pnx_algo_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) long timeout = data->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) while (timeout > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return (timeout <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct timer_list *timer = &alg_data->mif.timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long expires = msecs_to_jiffies(alg_data->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (expires <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) expires = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) del_timer_sync(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) jiffies, expires);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) timer->expires = jiffies + expires;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) add_timer(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * i2c_pnx_start - start a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @slave_addr: slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @adap: pointer to adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Generate a START signal in the desired mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int i2c_pnx_start(unsigned char slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) slave_addr, alg_data->mif.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Check for 7 bit slave addresses only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (slave_addr & ~0x7f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) alg_data->adapter.name, slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* First, make sure bus is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (wait_timeout(alg_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Somebody else is monopolizing the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) alg_data->adapter.name, slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ioread32(I2C_REG_CTL(alg_data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Sorry, we lost the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "%s: Arbitration failure. Slave addr = %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) alg_data->adapter.name, slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * OK, I2C is enabled and we have the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Clear the current TDI and AFI status flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (slave_addr << 1) | start_bit | alg_data->mif.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Write the slave address, START bit and R/W bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) I2C_REG_TX(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * i2c_pnx_stop - stop a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @adap: pointer to I2C adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Generate a STOP signal to terminate the master transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Only 1 msec max timeout due to interrupt context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) long timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Write a STOP bit to TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Wait until the STOP is seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) while (timeout > 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* may be called from interrupt context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * i2c_pnx_master_xmit - transmit data to slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @adap: pointer to I2C adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Sends one byte of data to the slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (alg_data->mif.len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* We still have something to talk about... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = *alg_data->mif.buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (alg_data->mif.len == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= stop_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) alg_data->mif.len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) iowrite32(val, I2C_REG_TX(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __func__, val, alg_data->mif.len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (alg_data->mif.len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (alg_data->last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Wait until the STOP is seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (wait_timeout(alg_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "The bus is still active after timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Disable master interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) del_timer_sync(&alg_data->mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "%s(): Waking up xfer routine.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else if (alg_data->mif.len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* zero-sized transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) i2c_pnx_stop(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Disable master interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Stop timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) del_timer_sync(&alg_data->mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "%s(): Waking up xfer routine after zero-xfer.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * i2c_pnx_master_rcv - receive data from slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @adap: pointer to I2C adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Reads one byte data from the slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Check, whether there is already data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * or we didn't 'ask' for it yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* 'Asking' is done asynchronously, e.g. dummy TX of several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * bytes is done before the first actual RX arrives in FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Therefore, ordered bytes (via TX) are counted separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (alg_data->mif.order) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "%s(): Write dummy data to fill Rx-fifo...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (alg_data->mif.order == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Last byte, do not acknowledge next rcv. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val |= stop_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Enable interrupt RFDAIE (data in Rx fifo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * and disable DRMIE (need data for Tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ctl = ioread32(I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ctl |= mcntrl_rffie | mcntrl_daie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ctl &= ~mcntrl_drmie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Now we'll 'ask' for data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * For each byte we want to receive, we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * write a (dummy) byte to the Tx-FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) iowrite32(val, I2C_REG_TX(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) alg_data->mif.order--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Handle data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (alg_data->mif.len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) val = ioread32(I2C_REG_RX(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *alg_data->mif.buf++ = (u8) (val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __func__, val, alg_data->mif.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) alg_data->mif.len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (alg_data->mif.len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (alg_data->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Wait until the STOP is seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (wait_timeout(alg_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "The bus is still active after timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Disable master interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ctl = ioread32(I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mcntrl_drmie | mcntrl_daie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Kill timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) del_timer_sync(&alg_data->mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct i2c_pnx_algo_data *alg_data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 stat, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) "%s(): mstat = %x mctrl = %x, mode = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ioread32(I2C_REG_STS(alg_data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ioread32(I2C_REG_CTL(alg_data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) alg_data->mif.mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) stat = ioread32(I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* let's see what kind of event this is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (stat & mstatus_afi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* We lost arbitration in the midst of a transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) alg_data->mif.ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Disable master interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctl = ioread32(I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mcntrl_drmie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Stop timer, to prevent timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) del_timer_sync(&alg_data->mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else if (stat & mstatus_nai) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Slave did not acknowledge, generate a STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "%s(): Slave did not acknowledge, generating a STOP.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) i2c_pnx_stop(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Disable master interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ctl = ioread32(I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mcntrl_drmie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Our return value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) alg_data->mif.ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Stop timer, to prevent timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) del_timer_sync(&alg_data->mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Two options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * - Master Tx needs data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * - There is data in the Rx-fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * The latter is only the case if we have requested for data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * via a dummy write. (See 'i2c_pnx_master_rcv'.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * We therefore check, as a sanity check, whether that interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * has been enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) i2c_pnx_master_xmit(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) i2c_pnx_master_rcv(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Clear TDI and AFI bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) stat = ioread32(I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "%s(): exiting, stat = %x ctrl = %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __func__, ioread32(I2C_REG_STS(alg_data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ioread32(I2C_REG_CTL(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void i2c_pnx_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct i2c_pnx_algo_data *alg_data = from_timer(alg_data, t, mif.timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ioread32(I2C_REG_STS(alg_data)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ioread32(I2C_REG_CTL(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Reset master and disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ctl = ioread32(I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ctl |= mcntrl_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) iowrite32(ctl, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) wait_reset(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) alg_data->mif.ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) complete(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "%s: Bus is still active after xfer. Reset it...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) alg_data->adapter.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) wait_reset(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* If there is data in the fifo's after transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * flush fifo's by reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) wait_reset(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else if (stat & mstatus_nai) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) wait_reset(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * i2c_pnx_xfer - generic transfer entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @adap: pointer to I2C adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @msgs: array of messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @num: number of messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * Initiates the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int rc = 0, completed = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct i2c_pnx_algo_data *alg_data = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "%s(): entering: %d messages, stat = %04x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __func__, num, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bus_reset_if_active(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Process transactions in a loop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (i = 0; rc >= 0 && i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) addr = pmsg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (pmsg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "%s: 10 bits addr not supported!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) alg_data->adapter.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) alg_data->mif.buf = pmsg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) alg_data->mif.len = pmsg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) alg_data->mif.order = pmsg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) I2C_SMBUS_READ : I2C_SMBUS_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) alg_data->mif.ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) alg_data->last = (i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __func__, alg_data->mif.mode, alg_data->mif.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) i2c_pnx_arm_timer(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* initialize the completion var */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) init_completion(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Enable master interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mcntrl_naie | mcntrl_drmie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Put start-code and slave-address on the bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) rc = i2c_pnx_start(addr, alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) wait_for_completion(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!(rc = alg_data->mif.ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) completed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "%s(): Complete, return code = %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __func__, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Clear TDI and AFI bits in case they are set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "%s: TDI still set... clearing now.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) alg_data->adapter.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) iowrite32(stat, I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(&alg_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "%s: AFI still set... clearing now.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) alg_data->adapter.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) iowrite32(stat, I2C_REG_STS(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) bus_reset_if_active(alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Cleanup to be sure... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) alg_data->mif.buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) alg_data->mif.len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) alg_data->mif.order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) __func__, ioread32(I2C_REG_STS(alg_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (completed != num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ((rc < 0) ? rc : -EREMOTEIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static u32 i2c_pnx_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const struct i2c_algorithm pnx_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .master_xfer = i2c_pnx_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .functionality = i2c_pnx_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int i2c_pnx_controller_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) clk_disable_unprepare(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int i2c_pnx_controller_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return clk_prepare_enable(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) i2c_pnx_controller_suspend, i2c_pnx_controller_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PNX_I2C_PM (&i2c_pnx_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PNX_I2C_PM NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int i2c_pnx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct i2c_pnx_algo_data *alg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!alg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) platform_set_drvdata(pdev, alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) alg_data->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) alg_data->adapter.algo = &pnx_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) alg_data->adapter.algo_data = alg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) alg_data->adapter.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) &speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * At this point, it is planned to add an OF timeout property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * As soon as there is a consensus about how to call and handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * this, sth. like the following can be put here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * of_property_read_u32(pdev->dev.of_node, "timeout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * &alg_data->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) alg_data->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (IS_ERR(alg_data->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return PTR_ERR(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) timer_setup(&alg_data->mif.timer, i2c_pnx_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "%s", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Register I/O resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) alg_data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (IS_ERR(alg_data->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return PTR_ERR(alg_data->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = clk_prepare_enable(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) freq = clk_get_rate(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * Clock Divisor High This value is the number of system clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * the serial clock (SCL) will be high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * For example, if the system clock period is 50 ns and the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * desired serial period is 10000 ns (100 kHz), then CLKHI would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * programmed into CLKHI will vary from this slightly due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * variations in the output pad's rise and fall times as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * the deglitching filter length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tmp = (freq / speed) / 2 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (tmp > 0x3FF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) tmp = 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) iowrite32(tmp, I2C_REG_CKH(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) iowrite32(tmp, I2C_REG_CKL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (wait_reset(alg_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto out_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) init_completion(&alg_data->mif.complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) alg_data->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (alg_data->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = alg_data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) goto out_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 0, pdev->name, alg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Register this adapter with the I2C subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ret = i2c_add_numbered_adapter(&alg_data->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) goto out_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_dbg(&pdev->dev, "%s: Master at %pap, irq %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) alg_data->adapter.name, &res->start, alg_data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) out_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) clk_disable_unprepare(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int i2c_pnx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) i2c_del_adapter(&alg_data->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) clk_disable_unprepare(alg_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct of_device_id i2c_pnx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { .compatible = "nxp,pnx-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static struct platform_driver i2c_pnx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .name = "pnx-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .of_match_table = of_match_ptr(i2c_pnx_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .pm = PNX_I2C_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .probe = i2c_pnx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .remove = i2c_pnx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int __init i2c_adap_pnx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return platform_driver_register(&i2c_pnx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void __exit i2c_adap_pnx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) platform_driver_unregister(&i2c_pnx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) MODULE_AUTHOR("Vitaly Wool");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MODULE_AUTHOR("Dennis Kovalev <source@mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MODULE_ALIAS("platform:pnx-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* We need to make sure I2C is initialized before USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) subsys_initcall(i2c_adap_pnx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) module_exit(i2c_adap_pnx_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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