^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2006-2007 PA Semi, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SMBus host driver for PA Semi PWRficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static struct pci_driver pasemi_smb_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct pasemi_smbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_MTXFIFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_MRXFIFO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_SMSTA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_CTL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Register defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MTXFIFO_READ 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MTXFIFO_STOP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MTXFIFO_START 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MTXFIFO_DATA_M 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MRXFIFO_EMPTY 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MRXFIFO_DATA_M 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SMSTA_XEN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SMSTA_MTN 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTL_MRR 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CTL_MTR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CTL_CLK_M 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_100K_DIV 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_400K_DIV 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_dbg(&smbus->dev->dev, "smbus write reg %lx val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) smbus->base + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) outl(val, smbus->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline int reg_read(struct pasemi_smbus *smbus, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = inl(smbus->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_dbg(&smbus->dev->dev, "smbus read reg %lx val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) smbus->base + reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RXFIFO_RD(smbus) reg_read((smbus), REG_MRXFIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void pasemi_smb_clear(struct pasemi_smbus *smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) status = reg_read(smbus, REG_SMSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg_write(smbus, REG_SMSTA, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int pasemi_smb_waitready(struct pasemi_smbus *smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) status = reg_read(smbus, REG_SMSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) while (!(status & SMSTA_XEN) && timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) status = reg_read(smbus, REG_SMSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Got NACK? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (status & SMSTA_MTN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (timeout < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_warn(&smbus->dev->dev, "Timeout, status 0x%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg_write(smbus, REG_SMSTA, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Clear XEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg_write(smbus, REG_SMSTA, SMSTA_XEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int pasemi_i2c_xfer_msg(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct i2c_msg *msg, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pasemi_smbus *smbus = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int read, i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) read = msg->flags & I2C_M_RD ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TXFIFO_WR(smbus, MTXFIFO_START | i2c_8bit_addr_from_msg(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) TXFIFO_WR(smbus, msg->len | MTXFIFO_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (stop ? MTXFIFO_STOP : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) err = pasemi_smb_waitready(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (rd & MRXFIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msg->buf[i] = rd & MRXFIFO_DATA_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0; i < msg->len - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) TXFIFO_WR(smbus, msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) TXFIFO_WR(smbus, msg->buf[msg->len-1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (stop ? MTXFIFO_STOP : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reset_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (CLK_100K_DIV & CTL_CLK_M)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int pasemi_i2c_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pasemi_smbus *smbus = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pasemi_smb_clear(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 0; i < num && !ret; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = pasemi_i2c_xfer_msg(adapter, &msgs[i], (i == (num - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int pasemi_smb_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u16 addr, unsigned short flags, char read_write, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct pasemi_smbus *smbus = adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int read_flag, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int len = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* All our ops take 8-bit shifted addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) addr <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) read_flag = read_write == I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pasemi_smb_clear(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) TXFIFO_WR(smbus, addr | read_flag | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (read_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) TXFIFO_WR(smbus, 1 | MTXFIFO_STOP | MTXFIFO_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TXFIFO_WR(smbus, MTXFIFO_STOP | command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) TXFIFO_WR(smbus, addr | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) TXFIFO_WR(smbus, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) TXFIFO_WR(smbus, 1 | MTXFIFO_READ | MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TXFIFO_WR(smbus, MTXFIFO_STOP | data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TXFIFO_WR(smbus, addr | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) TXFIFO_WR(smbus, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) TXFIFO_WR(smbus, 2 | MTXFIFO_READ | MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) TXFIFO_WR(smbus, MTXFIFO_STOP | (data->word >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) TXFIFO_WR(smbus, addr | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) TXFIFO_WR(smbus, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TXFIFO_WR(smbus, 1 | MTXFIFO_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) len = min_t(u8, (rd & MRXFIFO_DATA_M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) I2C_SMBUS_BLOCK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) TXFIFO_WR(smbus, len | MTXFIFO_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) TXFIFO_WR(smbus, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 1; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) TXFIFO_WR(smbus, data->block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TXFIFO_WR(smbus, data->block[len] | MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) read_write = I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TXFIFO_WR(smbus, addr | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TXFIFO_WR(smbus, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TXFIFO_WR(smbus, data->word & MTXFIFO_DATA_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TXFIFO_WR(smbus, (data->word >> 8) & MTXFIFO_DATA_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TXFIFO_WR(smbus, addr | I2C_SMBUS_READ | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TXFIFO_WR(smbus, 2 | MTXFIFO_STOP | MTXFIFO_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) len = min_t(u8, data->block[0], I2C_SMBUS_BLOCK_MAX - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) read_write = I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) TXFIFO_WR(smbus, addr | MTXFIFO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TXFIFO_WR(smbus, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) TXFIFO_WR(smbus, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 1; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) TXFIFO_WR(smbus, data->block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) TXFIFO_WR(smbus, addr | I2C_SMBUS_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TXFIFO_WR(smbus, MTXFIFO_READ | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) len = min_t(u8, (rd & MRXFIFO_DATA_M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) I2C_SMBUS_BLOCK_MAX - len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) TXFIFO_WR(smbus, len | MTXFIFO_READ | MTXFIFO_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_warn(&adapter->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err = pasemi_smb_waitready(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (rd & MRXFIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) data->byte = rd & MRXFIFO_DATA_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (rd & MRXFIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) data->word = rd & MRXFIFO_DATA_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (rd & MRXFIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) data->word |= (rd & MRXFIFO_DATA_M) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (i = 1; i <= len; i ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rd = RXFIFO_RD(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (rd & MRXFIFO_EMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) err = -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) goto reset_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->block[i] = rd & MRXFIFO_DATA_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reset_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (CLK_100K_DIV & CTL_CLK_M)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static u32 pasemi_smb_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) I2C_FUNC_SMBUS_BLOCK_PROC_CALL | I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .master_xfer = pasemi_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .smbus_xfer = pasemi_smb_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .functionality = pasemi_smb_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int pasemi_smb_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct pasemi_smbus *smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) smbus = kzalloc(sizeof(struct pasemi_smbus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) smbus->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) smbus->base = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) smbus->size = pci_resource_len(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!request_region(smbus->base, smbus->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pasemi_smb_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) error = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto out_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) smbus->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "PA Semi SMBus adapter at 0x%lx", smbus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) smbus->adapter.algo = &smbus_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) smbus->adapter.algo_data = smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* set up the sysfs linkage to our parent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) smbus->adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (CLK_100K_DIV & CTL_CLK_M)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) error = i2c_add_adapter(&smbus->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) goto out_release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pci_set_drvdata(dev, smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) out_release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) release_region(smbus->base, smbus->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) out_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) kfree(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static void pasemi_smb_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct pasemi_smbus *smbus = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) i2c_del_adapter(&smbus->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) release_region(smbus->base, smbus->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) kfree(smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct pci_device_id pasemi_smb_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { PCI_DEVICE(0x1959, 0xa003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_DEVICE_TABLE(pci, pasemi_smb_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct pci_driver pasemi_smb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .name = "i2c-pasemi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .id_table = pasemi_smb_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .probe = pasemi_smb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .remove = pasemi_smb_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) module_pci_driver(pasemi_smb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DESCRIPTION("PA Semi PWRficient SMBus driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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