Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Actions Semiconductor Owl SoC's I2C driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define OWL_I2C_REG_CTL		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define OWL_I2C_REG_CLKDIV	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define OWL_I2C_REG_STAT	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OWL_I2C_REG_ADDR	0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define OWL_I2C_REG_TXDAT	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define OWL_I2C_REG_RXDAT	0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define OWL_I2C_REG_CMD		0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OWL_I2C_REG_FIFOCTL	0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OWL_I2C_REG_FIFOSTAT	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OWL_I2C_REG_DATCNT	0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OWL_I2C_REG_RCNT	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* I2Cx_CTL Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OWL_I2C_CTL_RB		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OWL_I2C_CTL_GBCC(x)	(((x) & 0x3) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	OWL_I2C_CTL_GBCC_NONE	OWL_I2C_CTL_GBCC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	OWL_I2C_CTL_GBCC_START	OWL_I2C_CTL_GBCC(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	OWL_I2C_CTL_GBCC_STOP	OWL_I2C_CTL_GBCC(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	OWL_I2C_CTL_GBCC_RSTART	OWL_I2C_CTL_GBCC(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OWL_I2C_CTL_IRQE	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OWL_I2C_CTL_EN		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OWL_I2C_CTL_AE		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OWL_I2C_CTL_SHSM	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OWL_I2C_DIV_FACTOR(x)	((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* I2Cx_STAT Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OWL_I2C_STAT_RACK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OWL_I2C_STAT_BEB	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OWL_I2C_STAT_IRQP	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OWL_I2C_STAT_LAB	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OWL_I2C_STAT_STPD	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OWL_I2C_STAT_STAD	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OWL_I2C_STAT_BBB	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OWL_I2C_STAT_TCB	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OWL_I2C_STAT_LBST	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OWL_I2C_STAT_SAMB	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OWL_I2C_STAT_SRGC	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* I2Cx_CMD Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OWL_I2C_CMD_SBE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OWL_I2C_CMD_RBE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OWL_I2C_CMD_DE		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OWL_I2C_CMD_NS		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OWL_I2C_CMD_SE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define OWL_I2C_CMD_MSS		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OWL_I2C_CMD_WRS		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OWL_I2C_CMD_SECL	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OWL_I2C_CMD_AS(x)	(((x) & 0x7) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OWL_I2C_CMD_SAS(x)	(((x) & 0x7) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* I2Cx_FIFOCTL Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OWL_I2C_FIFOCTL_NIB	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OWL_I2C_FIFOCTL_RFR	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OWL_I2C_FIFOCTL_TFR	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* I2Cc_FIFOSTAT Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OWL_I2C_FIFOSTAT_RNB	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OWL_I2C_FIFOSTAT_RFE	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OWL_I2C_FIFOSTAT_TFF	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OWL_I2C_FIFOSTAT_TFD	GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OWL_I2C_FIFOSTAT_RFD	GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* I2C bus timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OWL_I2C_TIMEOUT		msecs_to_jiffies(4 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OWL_I2C_MAX_RETRIES	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct owl_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct i2c_adapter	adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct i2c_msg		*msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct completion	msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned long		clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32			bus_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32			msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int			err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	regval = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		regval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		regval &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel(regval, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			   OWL_I2C_CTL_EN, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			   OWL_I2C_CTL_EN, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Clear status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int val, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			   OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			   true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Wait 50ms for FIFO reset complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	} while (timeout++ < OWL_I2C_MAX_RETRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (timeout > OWL_I2C_MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* Set clock divider factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct owl_i2c_dev *i2c_dev = _dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct i2c_msg *msg = i2c_dev->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int stat, fifostat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	spin_lock(&i2c_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	i2c_dev->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Handle NACK from slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		i2c_dev->err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		/* Clear NACK error bit by writing "1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				   OWL_I2C_FIFOSTAT_RNB, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* Handle bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (stat & OWL_I2C_STAT_BEB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		i2c_dev->err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		/* Clear BUS error bit by writing "1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				   OWL_I2C_STAT_BEB, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Handle FIFO read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 							     OWL_I2C_REG_RXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		/* Handle the remaining bytes which were not sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			writel(msg->buf[i2c_dev->msg_ptr++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			       i2c_dev->base + OWL_I2C_REG_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			   OWL_I2C_STAT_IRQP, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	complete_all(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	spin_unlock(&i2c_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static u32 owl_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* Check for Bus busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	timeout = jiffies + OWL_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			dev_err(&adap->dev, "Bus busy timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			       int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned int i2c_cmd, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	spin_lock_irqsave(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Reset I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	owl_i2c_reset(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* Set bus frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	owl_i2c_set_freq(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * Spinlock should be released before calling reset FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * bus busy check since those functions may sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spin_unlock_irqrestore(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ret = owl_i2c_reset_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto unlocked_err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Check for bus busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = owl_i2c_check_bus_busy(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		goto unlocked_err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	spin_lock_irqsave(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Check for Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (val & OWL_I2C_STAT_LAB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		val &= ~OWL_I2C_STAT_LAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	reinit_completion(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Enable I2C controller interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			   OWL_I2C_CTL_IRQE, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	 * Select: FIFO enable, Master mode, Stop enable, Data count enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * Send start bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		  OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* Handle repeated start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (num > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		/* Set internal address length and enable repeated start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			   OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		/* Write slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		addr = i2c_8bit_addr_from_msg(&msgs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		/* Write internal register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		for (idx = 0; idx < msgs[0].len; idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			writel(msgs[0].buf[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			       i2c_dev->base + OWL_I2C_REG_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		msg = &msgs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		/* Set address length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		i2c_cmd |= OWL_I2C_CMD_AS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		msg = &msgs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	i2c_dev->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	i2c_dev->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* Set data count for the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (!(msg->flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		/* Write data to FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		for (idx = 0; idx < msg->len; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			/* Check for FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			    OWL_I2C_FIFOSTAT_TFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			writel(msg->buf[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			       i2c_dev->base + OWL_I2C_REG_TXDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		i2c_dev->msg_ptr = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* Ignore the NACK if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (msg->flags & I2C_M_IGNORE_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				   OWL_I2C_FIFOCTL_NIB, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				   OWL_I2C_FIFOCTL_NIB, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* Start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	spin_unlock_irqrestore(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 						adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	spin_lock_irqsave(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		dev_err(&adap->dev, "Transaction timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		/* Send stop condition and release the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				   OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				   true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	ret = i2c_dev->err < 0 ? i2c_dev->err : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	spin_unlock_irqrestore(&i2c_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unlocked_err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* Disable I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			   OWL_I2C_CTL_EN, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct i2c_algorithm owl_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.master_xfer    = owl_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.functionality  = owl_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct i2c_adapter_quirks owl_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.flags		= I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.max_read_len   = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.max_write_len  = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.max_comb_1st_msg_len = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.max_comb_2nd_msg_len = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int owl_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct owl_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (of_property_read_u32(dev->of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 				 &i2c_dev->bus_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	/* We support only frequencies of 100k and 400k for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	    i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	i2c_dev->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (IS_ERR(i2c_dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		dev_err(dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return PTR_ERR(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (!i2c_dev->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		dev_err(dev, "input clock rate should not be zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	init_completion(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	spin_lock_init(&i2c_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	i2c_dev->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	i2c_dev->adap.algo = &owl_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	i2c_dev->adap.quirks = &owl_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	i2c_dev->adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	i2c_dev->adap.dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		 "%s", "OWL I2C adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			       i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		dev_err(dev, "failed to request irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	return i2c_add_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct of_device_id owl_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	{ .compatible = "actions,s700-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	{ .compatible = "actions,s900-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct platform_driver owl_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.probe		= owl_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		.name	= "owl-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		.of_match_table = of_match_ptr(owl_i2c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) module_platform_driver(owl_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_LICENSE("GPL");