^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI OMAP I2C master mode driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 - 2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Originally written by MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Additional contributions by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Imre Deak <imre.deak@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Juha Yrjölä <juha.yrjola@solidboot.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Syed Khasim <x0khasim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Nishant Menon <nm@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/i2c-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* I2C controller revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP_I2C_OMAP1_REV_2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* I2C controller revisions present on specific hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP_I2C_REV_ON_2430 0x00000036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP_I2C_REV_ON_3630 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* timeout waiting for the controller to respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* timeout for pm runtime autosuspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* timeout for making decision on bus free status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) OMAP_I2C_REV_REG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) OMAP_I2C_IE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) OMAP_I2C_STAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) OMAP_I2C_IV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) OMAP_I2C_WE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) OMAP_I2C_SYSS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) OMAP_I2C_BUF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) OMAP_I2C_CNT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) OMAP_I2C_DATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) OMAP_I2C_SYSC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OMAP_I2C_CON_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) OMAP_I2C_OA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) OMAP_I2C_SA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) OMAP_I2C_PSC_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) OMAP_I2C_SCLL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) OMAP_I2C_SCLH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) OMAP_I2C_SYSTEST_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) OMAP_I2C_BUFSTAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* only on OMAP4430 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) OMAP_I2C_IP_V2_REVNB_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OMAP_I2C_IP_V2_REVNB_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) OMAP_I2C_IP_V2_IRQSTATUS_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) OMAP_I2C_IP_V2_IRQENABLE_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) OMAP_I2C_IP_V2_IRQENABLE_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* I2C Status Register (OMAP_I2C_STAT): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* I2C WE wakeup enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* I2C Configuration Register (OMAP_I2C_CON): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* I2C SCL time value when Master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP_I2C_SCLL_HSSCLL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP_I2C_SCLH_HSSCLH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* I2C System Test Register (OMAP_I2C_SYSTEST): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Functional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* SDA/SCL IO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* OCP_SYSSTATUS bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SYSS_RESETDONE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* OCP_SYSCONFIG bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SYSC_SIDLEMODE_MASK (0x3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SYSC_ENAWAKEUP_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SYSC_SOFTRESET_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SYSC_AUTOIDLE_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SYSC_IDLEMODE_SMART 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SYSC_CLOCKACTIVITY_FCLK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Errata definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define I2C_OMAP_ERRATA_I207 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define I2C_OMAP_ERRATA_I462 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct omap_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __iomem *base; /* virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int reg_shift; /* bit shift for I2C register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct resource *ioarea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 latency; /* maximum mpu wkup latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void (*set_mpu_wkup_lat)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) long latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 speed; /* Speed of bus in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 scheme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u8 fifo_size; /* use as flag and value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * fifo_size==0 implies no fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * if set, should be trsh+1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned b_hw:1; /* bad h/w fixes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned bb_valid:1; /* true when BB-bit reflects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * the I2C bus state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned receiver:1; /* true when we're in receiver mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u16 iestate; /* Saved interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u16 pscstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u16 scllstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u16 sclhstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u16 syscstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 westate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const u8 reg_map_ip_v1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [OMAP_I2C_REV_REG] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [OMAP_I2C_IE_REG] = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [OMAP_I2C_STAT_REG] = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [OMAP_I2C_IV_REG] = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [OMAP_I2C_WE_REG] = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [OMAP_I2C_SYSS_REG] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [OMAP_I2C_BUF_REG] = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [OMAP_I2C_CNT_REG] = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [OMAP_I2C_DATA_REG] = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [OMAP_I2C_SYSC_REG] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [OMAP_I2C_CON_REG] = 0x09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [OMAP_I2C_OA_REG] = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [OMAP_I2C_SA_REG] = 0x0b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [OMAP_I2C_PSC_REG] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [OMAP_I2C_SCLL_REG] = 0x0d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [OMAP_I2C_SCLH_REG] = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [OMAP_I2C_SYSTEST_REG] = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [OMAP_I2C_BUFSTAT_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const u8 reg_map_ip_v2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [OMAP_I2C_REV_REG] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [OMAP_I2C_IE_REG] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [OMAP_I2C_STAT_REG] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [OMAP_I2C_IV_REG] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [OMAP_I2C_WE_REG] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [OMAP_I2C_SYSS_REG] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [OMAP_I2C_BUF_REG] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [OMAP_I2C_CNT_REG] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [OMAP_I2C_DATA_REG] = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [OMAP_I2C_SYSC_REG] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [OMAP_I2C_CON_REG] = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [OMAP_I2C_OA_REG] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [OMAP_I2C_SA_REG] = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [OMAP_I2C_PSC_REG] = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [OMAP_I2C_SCLL_REG] = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [OMAP_I2C_SCLH_REG] = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [OMAP_I2C_SYSTEST_REG] = 0xbC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [OMAP_I2C_BUFSTAT_REG] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writew_relaxed(val, omap->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) (omap->regs[reg] << omap->reg_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return readw_relaxed(omap->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (omap->regs[reg] << omap->reg_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void __omap_i2c_init(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* SCL low and high time values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Take the I2C module out of reset: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * bus is busy. It will be changed to 1 on the next IP FCLK clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * udelay(1) will be enough to fix that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Don't write to this register if the IE state is 0 as it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * cause deadlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (omap->iestate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int omap_i2c_reset(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u16 sysc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Disable I2C controller before soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ~(OMAP_I2C_CON_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* For some reason we need to set the EN bit before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * reset done bit gets set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) timeout = jiffies + OMAP_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SYSS_RESETDONE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_warn(omap->dev, "timeout waiting "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "for controller reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* SYSC register is cleared by the reset; rewrite it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Schedule I2C-bus monitoring on the next transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) omap->bb_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int omap_i2c_init(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u16 psc = 0, scll = 0, sclh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned long fclk_rate = 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long internal_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Enabling all wakup sources to stop I2C freezing on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * WFI instruction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * REVISIT: Some wkup sources might not be needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) omap->westate = OMAP_I2C_WE_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * The I2C functional clock is the armxor_ck, so there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * no need to get "armxor_ck" separately. Now, if OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * always returns 12MHz for the functional clock, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * do this bit unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fclk = clk_get(omap->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (IS_ERR(fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) error = PTR_ERR(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(omap->dev, "could not get fck: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fclk_rate = clk_get_rate(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) clk_put(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* TRM for 5912 says the I2C clock must be prescaled to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * between 7 - 12 MHz. The XOR input clock is typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * 12, 13 or 19.2 MHz. So we should have code that produces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * XOR MHz Divider Prescaler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * 12 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * 13 2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * 19.2 2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (fclk_rate > 12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) psc = fclk_rate / 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * HSI2C controller internal clk rate should be 19.2 Mhz for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * HS and for all modes on 2430. On 34xx we can use lower rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * to get longer filter period for better noise suppression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * The filter is iclk (fclk for HS) period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (omap->speed > 400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) internal_clk = 19200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else if (omap->speed > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) internal_clk = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) internal_clk = 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) fclk = clk_get(omap->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (IS_ERR(fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) error = PTR_ERR(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(omap->dev, "could not get fck: %i\n", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fclk_rate = clk_get_rate(fclk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_put(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Compute prescaler divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) psc = fclk_rate / internal_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) psc = psc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* If configured for High Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (omap->speed > 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long scl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* For first phase of HS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) scl = internal_clk / 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fsscll = scl - (scl / 3) - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) fssclh = (scl / 3) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* For second phase of HS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) scl = fclk_rate / omap->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) hsscll = scl - (scl / 3) - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hssclh = (scl / 3) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else if (omap->speed > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long scl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) scl = internal_clk / omap->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) fsscll = scl - (scl / 3) - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) fssclh = (scl / 3) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) fsscll = internal_clk / (omap->speed * 2) - 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) fssclh = internal_clk / (omap->speed * 2) - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Program desired operating rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fclk_rate /= (psc + 1) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (psc > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) psc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) scll = fclk_rate / (omap->speed * 2) - 7 + psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) omap->pscstate = psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) omap->scllstate = scll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) omap->sclhstate = sclh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) omap->bb_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __omap_i2c_init(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Try bus recovery, but only if SDA is actually low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u16 systest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0; /* bus seems to already be fine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EBUSY; /* recovery would not fix SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return i2c_recover_bus(&omap->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Waiting on Bus Busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) timeout = jiffies + OMAP_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return omap_i2c_recover_bus(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Wait while BB-bit doesn't reflect the I2C bus state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * In a multimaster environment, after IP software reset, BB-bit value doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * correspond to the current bus state. It may happen what BB-bit will be 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * while the bus is busy due to another I2C master activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Here are BB-bit values after reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * SDA SCL BB NOTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * 0 0 0 1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * 1 0 0 1, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * 0 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * 1 1 0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * combinations on the bus, it set BB-bit to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * it set BB-bit to 0 and BF to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * BB and BF bits correctly tracks the bus state while IP is suspended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * BB bit became valid on the next FCLK clock after CON_EN bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * 1. Any transfer started when BB=0 and bus is busy wouldn't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * completed by IP and results in controller timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * 2. Any transfer started when BB=0 and SCL=0 results in IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * starting to drive SDA low. In that case IP corrupt data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * 3. Any transfer started in the middle of another master's transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * results in unpredictable results and data corruption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long bus_free_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int bus_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u16 stat, systest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (omap->bb_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) timeout = jiffies + OMAP_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * We will see BB or BF event in a case IP had detected any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * activity on the I2C bus. Now IP correctly tracks the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * state. BB-bit value is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Otherwise, we must look signals on the bus to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * the right decision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!bus_free) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bus_free_timeout = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) OMAP_I2C_BUS_FREE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bus_free = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * SDA and SCL lines was high for 10 ms without bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * activity detected. The bus is free. Consider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * BB-bit value is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (time_after(jiffies, bus_free_timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bus_free = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * SDA or SCL were low for the entire timeout without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * any activity detected. Most likely, a slave is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * locking up the bus with no master driving the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_warn(omap->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return omap_i2c_recover_bus(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) omap->bb_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u16 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Set up notification threshold based on message size. We're doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * this to try and avoid draining feature as much as possible. Whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * we have big messages to transfer (bigger than our total fifo size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * then we might use draining feature to transfer the remaining bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (is_rx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Clear RX Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) buf &= ~(0x3f << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Clear TX Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) buf &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (omap->rev < OMAP_I2C_REV_ON_3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) omap->b_hw = 1; /* Enable hardware fixes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* calculate wakeup latency constraint for MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (omap->set_mpu_wkup_lat != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) omap->latency = (1000000 * omap->threshold) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) (1000 * omap->speed / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void omap_i2c_wait(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u16 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) } while (!(stat & mask) && count < 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Low level master read/write transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct i2c_msg *msg, int stop, bool polling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) msg->addr, msg->len, msg->flags, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) omap->receiver = !!(msg->flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) omap->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) omap->buf_len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* make sure writes to omap->buf_len are ordered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Clear the FIFO Buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!polling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) reinit_completion(&omap->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) omap->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* High speed configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (omap->speed > 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) w |= OMAP_I2C_CON_OPMODE_HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (msg->flags & I2C_M_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) stop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (msg->flags & I2C_M_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) w |= OMAP_I2C_CON_XA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!(msg->flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) w |= OMAP_I2C_CON_TRX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!omap->b_hw && stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) w |= OMAP_I2C_CON_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * NOTE: STAT_BB bit could became 1 here if another master occupy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * the bus. IP successfully complete transfer when the bus will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * free again (BB reset to 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * Don't write stt and stp together on some hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (omap->b_hw && stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) while (con & OMAP_I2C_CON_STT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Let the user know if i2c is in a bad state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (time_after(jiffies, delay)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_err(omap->dev, "controller timed out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "waiting for start condition to finish\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) w |= OMAP_I2C_CON_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) w &= ~OMAP_I2C_CON_STT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * REVISIT: We should abort the transfer on signals, but the bus goes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * into arbitration and we're currently unable to recover from it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!polling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) timeout = wait_for_completion_timeout(&omap->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) OMAP_I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) omap_i2c_wait(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = omap_i2c_xfer_data(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) } while (ret == -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) timeout = !ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_err(omap->dev, "controller timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) omap_i2c_reset(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __omap_i2c_init(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (likely(!omap->cmd_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* We have an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) omap_i2c_reset(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __omap_i2c_init(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (omap->cmd_err & OMAP_I2C_STAT_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (msg->flags & I2C_M_IGNORE_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) w |= OMAP_I2C_CON_STP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * Prepare controller for a transaction and call omap_i2c_xfer_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * to do the work during IRQ processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) bool polling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) r = pm_runtime_get_sync(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) r = omap_i2c_wait_for_bb_valid(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) r = omap_i2c_wait_for_bb(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (omap->set_mpu_wkup_lat != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) omap->set_mpu_wkup_lat(omap->dev, omap->latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) polling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (r != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (r == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) r = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) omap_i2c_wait_for_bb(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (omap->set_mpu_wkup_lat != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) omap->set_mpu_wkup_lat(omap->dev, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) pm_runtime_mark_last_busy(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) pm_runtime_put_autosuspend(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return omap_i2c_xfer_common(adap, msgs, num, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return omap_i2c_xfer_common(adap, msgs, num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) omap_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) omap->cmd_err |= err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) complete(&omap->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Not applicable for OMAP4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Under certain rare conditions, RDR could be set again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * when the bus is busy, then ignore the interrupt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * clear the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (stat & OMAP_I2C_STAT_RDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Step 1: If RDR is set, clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Step 2: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) & OMAP_I2C_STAT_BB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Step 3: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) & OMAP_I2C_STAT_RDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_dbg(omap->dev, "RDR when bus is busy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* rev1 devices are apparently only on some 15xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #ifdef CONFIG_ARCH_OMAP15XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) omap_i2c_omap1_isr(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct omap_i2c_dev *omap = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u16 iv, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (pm_runtime_suspended(omap->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (iv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case 0x00: /* None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case 0x01: /* Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dev_err(omap->dev, "Arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case 0x02: /* No acknowledgement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case 0x03: /* Register access ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) omap_i2c_complete_cmd(omap, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) case 0x04: /* Receive data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (omap->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) *omap->buf++ = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (omap->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *omap->buf++ = w >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev_err(omap->dev, "RRDY IRQ while no data requested\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case 0x05: /* Transmit data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (omap->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) w = *omap->buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (omap->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) w |= *omap->buf++ << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(omap->dev, "XRDY IRQ while no data to send\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define omap_i2c_omap1_isr NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * data to DATA_REG. Otherwise some data bytes can be lost while transferring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * them from the memory to the I2C interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int errata_omap3_i462(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned long timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u16 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (stat & OMAP_I2C_STAT_XUDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) OMAP_I2C_STAT_XDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (stat & OMAP_I2C_STAT_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) omap->cmd_err |= OMAP_I2C_STAT_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (stat & OMAP_I2C_STAT_AL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_err(omap->dev, "Arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) omap->cmd_err |= OMAP_I2C_STAT_AL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev_err(omap->dev, "timeout waiting on XUDF bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) bool is_rdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) while (num_bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) *omap->buf++ = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Data reg in 2430, omap3 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * omap4 is 8 bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *omap->buf++ = w >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) bool is_xdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) while (num_bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) w = *omap->buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Data reg in 2430, omap3 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * omap4 is 8 bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) w |= *omap->buf++ << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) omap->buf_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (omap->errata & I2C_OMAP_ERRATA_I462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ret = errata_omap3_i462(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) omap_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct omap_i2c_dev *omap = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u16 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (stat & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u16 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u16 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int err = 0, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) stat &= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* If we're in receiver mode, ignore XDR/XRDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (omap->receiver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (!stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* my work here is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (count++ == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev_warn(omap->dev, "Too much work in one IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (stat & OMAP_I2C_STAT_NACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) err |= OMAP_I2C_STAT_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (stat & OMAP_I2C_STAT_AL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dev_err(omap->dev, "Arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) err |= OMAP_I2C_STAT_AL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * ProDB0017052: Clear ARDY bit twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (stat & OMAP_I2C_STAT_ARDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) OMAP_I2C_STAT_AL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) OMAP_I2C_STAT_RDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) OMAP_I2C_STAT_XRDY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) OMAP_I2C_STAT_XDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) OMAP_I2C_STAT_ARDY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (stat & OMAP_I2C_STAT_RDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u8 num_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (omap->fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) num_bytes = omap->buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (omap->errata & I2C_OMAP_ERRATA_I207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) i2c_omap_errata_i207(omap, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) num_bytes = (omap_i2c_read_reg(omap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) omap_i2c_receive_data(omap, num_bytes, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (stat & OMAP_I2C_STAT_RRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u8 num_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (omap->threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) num_bytes = omap->threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) omap_i2c_receive_data(omap, num_bytes, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (stat & OMAP_I2C_STAT_XDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u8 num_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (omap->fifo_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) num_bytes = omap->buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = omap_i2c_transmit_data(omap, num_bytes, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (stat & OMAP_I2C_STAT_XRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 num_bytes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (omap->threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) num_bytes = omap->threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = omap_i2c_transmit_data(omap, num_bytes, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (stat & OMAP_I2C_STAT_ROVR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) dev_err(omap->dev, "Receive overrun\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err |= OMAP_I2C_STAT_ROVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (stat & OMAP_I2C_STAT_XUDF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_err(omap->dev, "Transmit underflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) err |= OMAP_I2C_STAT_XUDF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) } while (stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) omap_i2c_isr_thread(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct omap_i2c_dev *omap = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = omap_i2c_xfer_data(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ret != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) omap_i2c_complete_cmd(omap, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static const struct i2c_algorithm omap_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .master_xfer = omap_i2c_xfer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .master_xfer_atomic = omap_i2c_xfer_polling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .functionality = omap_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const struct i2c_adapter_quirks omap_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static struct omap_i2c_bus_platform_data omap2420_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .rev = OMAP_I2C_IP_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .flags = OMAP_I2C_FLAG_NO_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) OMAP_I2C_FLAG_SIMPLE_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) OMAP_I2C_FLAG_16BIT_DATA_REG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) OMAP_I2C_FLAG_BUS_SHIFT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static struct omap_i2c_bus_platform_data omap2430_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .rev = OMAP_I2C_IP_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static struct omap_i2c_bus_platform_data omap3_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .rev = OMAP_I2C_IP_VERSION_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static struct omap_i2c_bus_platform_data omap4_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .rev = OMAP_I2C_IP_VERSION_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const struct of_device_id omap_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .compatible = "ti,omap4-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .data = &omap4_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .compatible = "ti,omap3-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .data = &omap3_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .compatible = "ti,omap2430-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .data = &omap2430_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .compatible = "ti,omap2420-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .data = &omap2420_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define OMAP_I2C_SCHEME_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define OMAP_I2C_SCHEME_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static int omap_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int omap_i2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) reg |= OMAP_I2C_SYSTEST_SCL_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) reg &= ~OMAP_I2C_SYSTEST_SCL_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* enable test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) reg |= OMAP_I2C_SYSTEST_ST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* select SDA/SCL IO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* set SCL to high-impedance state (reset value is 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) reg |= OMAP_I2C_SYSTEST_SCL_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* set SDA to high-impedance state (reset value is 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) reg |= OMAP_I2C_SYSTEST_SDA_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* restore reset values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) reg &= ~OMAP_I2C_SYSTEST_ST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) reg &= ~OMAP_I2C_SYSTEST_SCL_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) reg &= ~OMAP_I2C_SYSTEST_SDA_O;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .get_scl = omap_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .get_sda = omap_i2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .set_scl = omap_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .prepare_recovery = omap_i2c_prepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .unprepare_recovery = omap_i2c_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) omap_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct omap_i2c_dev *omap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) const struct omap_i2c_bus_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u16 minor, major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!omap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) omap->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (IS_ERR(omap->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return PTR_ERR(omap->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) u32 freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) omap->flags = pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) of_property_read_u32(node, "clock-frequency", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* convert DT freq value in Hz into kHz for speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) omap->speed = freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) } else if (pdata != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) omap->speed = pdata->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) omap->flags = pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) omap->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) omap->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) platform_set_drvdata(pdev, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) init_completion(&omap->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pm_runtime_enable(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) pm_runtime_use_autosuspend(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) r = pm_runtime_resume_and_get(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) goto err_disable_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * Also since the omap_i2c_read_reg uses reg_map_ip_* a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * readw_relaxed is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) rev = readw_relaxed(omap->base + 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) omap->scheme = OMAP_I2C_SCHEME(rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) switch (omap->scheme) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case OMAP_I2C_SCHEME_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) omap->regs = (u8 *)reg_map_ip_v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) case OMAP_I2C_SCHEME_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) omap->regs = (u8 *)reg_map_ip_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) rev = (rev << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) omap->rev = rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) omap->errata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) omap->errata |= I2C_OMAP_ERRATA_I207;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) omap->errata |= I2C_OMAP_ERRATA_I462;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) u16 s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* Set up the fifo size - Get total size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) omap->fifo_size = 0x8 << s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * Set up notification threshold as half the total available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * size. This is to ensure that we can handle the status on int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * call back latencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) omap->fifo_size = (omap->fifo_size / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (omap->rev < OMAP_I2C_REV_ON_3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) omap->b_hw = 1; /* Enable hardware fixes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* calculate wakeup latency constraint for MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (omap->set_mpu_wkup_lat != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) omap->latency = (1000000 * omap->fifo_size) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) (1000 * omap->speed / 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* reset ASAP, clearing any IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) omap_i2c_init(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (omap->rev < OMAP_I2C_OMAP1_REV_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) IRQF_NO_SUSPEND, pdev->name, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) r = devm_request_threaded_irq(&pdev->dev, omap->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) omap_i2c_isr, omap_i2c_isr_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) IRQF_NO_SUSPEND | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) pdev->name, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) adap = &omap->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) i2c_set_adapdata(adap, omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) adap->algo = &omap_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) adap->quirks = &omap_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* i2c device drivers may be active on return from add_adapter() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) r = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) goto err_unuse_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) major, minor, omap->speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) pm_runtime_mark_last_busy(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pm_runtime_put_autosuspend(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) err_unuse_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pm_runtime_dont_use_autosuspend(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pm_runtime_put_sync(omap->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) err_disable_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int omap_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) i2c_del_adapter(&omap->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) ret = pm_runtime_resume_and_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct omap_i2c_dev *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (omap->scheme == OMAP_I2C_SCHEME_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) OMAP_I2C_IP_V2_INTERRUPTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* Flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static int __maybe_unused omap_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) struct omap_i2c_dev *omap = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!omap->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) __omap_i2c_init(omap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static const struct dev_pm_ops omap_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) omap_i2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static struct platform_driver omap_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .probe = omap_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .remove = omap_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .name = "omap_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .pm = &omap_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .of_match_table = of_match_ptr(omap_i2c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* I2C may be needed to bring up other drivers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) omap_i2c_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return platform_driver_register(&omap_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) subsys_initcall(omap_i2c_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static void __exit omap_i2c_exit_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) platform_driver_unregister(&omap_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) module_exit(omap_i2c_exit_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) MODULE_ALIAS("platform:omap_i2c");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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