Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * (C) Copyright 2009-2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/octeon/octeon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "i2c-octeon-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRV_NAME "i2c-octeon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * octeon_i2c_int_enable - enable the CORE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @i2c: The struct octeon_i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * The interrupt will be asserted when there is non-STAT_IDLE state in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * the SW_TWSI_EOP_TWSI_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	octeon_i2c_write_int(i2c, TWSI_INT_CORE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* disable the CORE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* clear TS/ST/IFLG events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	octeon_i2c_write_int(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * octeon_i2c_int_enable78 - enable the CORE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @i2c: The struct octeon_i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * The interrupt will be asserted when there is non-STAT_IDLE state in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * SW_TWSI_EOP_TWSI_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	atomic_inc_return(&i2c->int_enable_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	enable_irq(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * The interrupt can be disabled in two places, but we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * want to make the disable_irq_nosync() call once, so keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * track with the atomic variable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	count = atomic_dec_if_positive(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (count >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* disable the CORE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__octeon_i2c_irq_disable(&i2c->int_enable_cnt, i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * octeon_i2c_hlc_int_enable78 - enable the ST interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * @i2c: The struct octeon_i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * The interrupt will be asserted when there is non-STAT_IDLE state in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * the SW_TWSI_EOP_TWSI_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	atomic_inc_return(&i2c->hlc_int_enable_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	enable_irq(i2c->hlc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* disable the ST interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	__octeon_i2c_irq_disable(&i2c->hlc_int_enable_cnt, i2c->hlc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* HLC interrupt service routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct octeon_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	i2c->hlc_int_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	wake_up(&i2c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	       I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct i2c_algorithm octeon_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.master_xfer = octeon_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.functionality = octeon_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct i2c_adapter octeon_i2c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.name = "OCTEON adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.algo = &octeon_i2c_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int octeon_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int irq, result = 0, hlc_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct octeon_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	bool cn78xx_style;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (cn78xx_style) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		hlc_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		if (hlc_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			return hlc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		irq = platform_get_irq(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* All adaptors have an irq.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (!i2c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	i2c->roff.sw_twsi = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	i2c->roff.twsi_int = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	i2c->roff.sw_twsi_ext = 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	i2c->twsi_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (IS_ERR(i2c->twsi_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		result = PTR_ERR(i2c->twsi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * "clock-rate" is a legacy binding, the official binding is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * "clock-frequency".  Try the official one first and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * fall back if it doesn't exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (of_property_read_u32(node, "clock-frequency", &i2c->twsi_freq) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	    of_property_read_u32(node, "clock-rate", &i2c->twsi_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			"no I2C 'clock-rate' or 'clock-frequency' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	i2c->sys_freq = octeon_get_io_clock_rate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	init_waitqueue_head(&i2c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	i2c->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (cn78xx_style) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		i2c->hlc_irq = hlc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		i2c->int_enable = octeon_i2c_int_enable78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		i2c->int_disable = octeon_i2c_int_disable78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		i2c->hlc_int_enable = octeon_i2c_hlc_int_enable78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		i2c->hlc_int_disable = octeon_i2c_hlc_int_disable78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					  octeon_i2c_hlc_isr78, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					  DRV_NAME, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			dev_err(i2c->dev, "failed to attach interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		i2c->int_enable = octeon_i2c_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		i2c->int_disable = octeon_i2c_int_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		i2c->hlc_int_enable = octeon_i2c_hlc_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		i2c->hlc_int_disable = octeon_i2c_int_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	result = devm_request_irq(&pdev->dev, i2c->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				  octeon_i2c_isr, 0, DRV_NAME, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		dev_err(i2c->dev, "failed to attach interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (OCTEON_IS_MODEL(OCTEON_CN38XX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		i2c->broken_irq_check = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	result = octeon_i2c_init_lowlevel(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		dev_err(i2c->dev, "init low level failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		goto  out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	octeon_i2c_set_clock(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	i2c->adap = octeon_i2c_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	i2c->adap.timeout = msecs_to_jiffies(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	i2c->adap.retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	i2c->adap.bus_recovery_info = &octeon_i2c_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	i2c->adap.dev.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	result = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dev_info(i2c->dev, "probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int octeon_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct octeon_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct of_device_id octeon_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	{ .compatible = "cavium,octeon-3860-twsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ .compatible = "cavium,octeon-7890-twsi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DEVICE_TABLE(of, octeon_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct platform_driver octeon_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe		= octeon_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.remove		= octeon_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.name	= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.of_match_table = octeon_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(octeon_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL");