^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Nvidia GPU I2C controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Ajay Gupta <ajayg@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* I2C definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2C_MST_CNTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2C_MST_CNTL_GEN_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_MST_CNTL_GEN_STOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2C_MST_CNTL_CMD_READ (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2C_MST_CNTL_CMD_WRITE (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_MST_CNTL_GEN_NACK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_MST_CNTL_STATUS GENMASK(30, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_MST_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_MST_I2C0_TIMING 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_MST_DATA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_MST_HYBRID_PADCTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct gpu_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct i2c_board_info *gpu_ccgx_ucsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct i2c_client *ccgx_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* enable 100KHZ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 500, 1000 * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(i2cd->dev, "i2c timeout error %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = readl(i2cd->regs + I2C_MST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (val & I2C_MST_CNTL_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case I2C_MST_CNTL_STATUS_OKAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) case I2C_MST_CNTL_STATUS_NO_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case I2C_MST_CNTL_STATUS_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(val, i2cd->regs + I2C_MST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) status = gpu_i2c_check_status(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = readl(i2cd->regs + I2C_MST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) data[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) put_unaligned_be16(val, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) put_unaligned_be24(val, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) put_unaligned_be32(val, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return gpu_i2c_check_status(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return gpu_i2c_check_status(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(data, i2cd->regs + I2C_MST_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(val, i2cd->regs + I2C_MST_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return gpu_i2c_check_status(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int status, status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool send_stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * The controller supports maximum 4 byte read due to known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * limitation of sending STOP after every read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pm_runtime_get_sync(i2cd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* program client address before starting read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* gpu_i2c_read has implicit start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 addr = i2c_8bit_addr_from_msg(msgs + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) status = gpu_i2c_start(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) send_stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) status = gpu_i2c_write(i2cd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (j = 0; j < msgs[i].len; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) send_stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) status = gpu_i2c_stop(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) status = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (send_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) status2 = gpu_i2c_stop(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (status2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pm_runtime_mark_last_busy(i2cd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pm_runtime_put_autosuspend(i2cd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct i2c_adapter_quirks gpu_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .max_read_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .max_comb_2nd_msg_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct i2c_algorithm gpu_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .master_xfer = gpu_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .functionality = gpu_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This driver is for Nvidia GPU cards with USB Type-C interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * We want to identify the cards using vendor ID and class code only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * to avoid dependency of adding product id for any new card which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * requires this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Currently there is no class code defined for UCSI device over PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * so using UNKNOWN class for now and it will be updated when UCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * over PCI gets a class code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * There is no other NVIDIA cards with UNKNOWN class code. Even if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * driver gets loaded for an undesired card then eventually i2c_read()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * (initiated from UCSI i2c_client) will timeout or UCSI commands will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct pci_device_id gpu_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct property_entry ccgx_props[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Use FW built for NVIDIA (nv) only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sizeof(*i2cd->gpu_ccgx_ucsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!i2cd->gpu_ccgx_ucsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sizeof(i2cd->gpu_ccgx_ucsi->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) i2cd->gpu_ccgx_ucsi->addr = 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) i2cd->gpu_ccgx_ucsi->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return PTR_ERR_OR_ZERO(i2cd->ccgx_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct gpu_i2c_dev *i2cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!i2cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) i2cd->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_set_drvdata(&pdev->dev, i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) status = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) i2cd->regs = pcim_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!i2cd->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(&pdev->dev, "pcim_iomap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gpu_enable_i2c_bus(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) i2c_set_adapdata(&i2cd->adapter, i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) i2cd->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sizeof(i2cd->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i2cd->adapter.algo = &gpu_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) i2cd->adapter.quirks = &gpu_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2cd->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) status = i2c_add_adapter(&i2cd->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) goto free_irq_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) status = gpu_populate_client(i2cd, pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto del_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) del_adapter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) i2c_del_adapter(&i2cd->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) free_irq_vectors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void gpu_i2c_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pm_runtime_get_noresume(i2cd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) i2c_del_adapter(&i2cd->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * correctly. Without it, lspci shows runtime pm status as "D0" for the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Documentation/power/pci.rst also insists for driver to provide this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static __maybe_unused int gpu_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static __maybe_unused int gpu_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gpu_enable_i2c_bus(i2cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Runtime resume ccgx client so that it can see for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * connector change event. Old ccg firmware has known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * issue of not triggering interrupt when a device is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * connected to runtime resume the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pm_request_resume(&i2cd->ccgx_client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct pci_driver gpu_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "nvidia-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .id_table = gpu_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .probe = gpu_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .remove = gpu_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pm = &gpu_i2c_driver_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) module_pci_driver(gpu_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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