^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Nuvoton NPCM7xx I2C Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum i2c_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) I2C_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) I2C_SLAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * External I2C Interface driver xfer indication values, which indicate status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * of the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum i2c_state_ind {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) I2C_NO_STATUS_IND = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) I2C_SLAVE_RCV_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) I2C_SLAVE_XMIT_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) I2C_SLAVE_XMIT_MISSING_DATA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) I2C_SLAVE_RESTART_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) I2C_SLAVE_DONE_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) I2C_MASTER_DONE_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) I2C_NACK_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) I2C_BUS_ERR_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) I2C_WAKE_UP_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) I2C_BLOCK_BYTES_ERR_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) I2C_SLAVE_RCV_MISSING_DATA_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Operation type values (used to define the operation currently running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * module is interrupt driven, on each interrupt the current operation is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * checked to see if the module is currently reading or writing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) enum i2c_oper {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) I2C_NO_OPER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) I2C_WRITE_OPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) I2C_READ_OPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* I2C Bank (module had 2 banks of registers) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum i2c_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) I2C_BANK_0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) I2C_BANK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Internal I2C states values (for the I2C module state machine). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) I2C_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) I2C_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) I2C_MASTER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) I2C_SLAVE_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) I2C_OPER_STARTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) I2C_STOP_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Module supports setting multiple own slave addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum i2c_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) I2C_SLAVE_ADDR1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) I2C_SLAVE_ADDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) I2C_SLAVE_ADDR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) I2C_SLAVE_ADDR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) I2C_SLAVE_ADDR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) I2C_SLAVE_ADDR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) I2C_SLAVE_ADDR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) I2C_SLAVE_ADDR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) I2C_SLAVE_ADDR9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) I2C_SLAVE_ADDR10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) I2C_GC_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) I2C_ARP_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* init register and default value required to enable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NPCM_I2CSEGCTL 0xE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Common regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NPCM_I2CSDA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NPCM_I2CST 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NPCM_I2CCST 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NPCM_I2CCTL1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define NPCM_I2CADDR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define NPCM_I2CCTL2 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define NPCM_I2CADDR2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define NPCM_I2CCTL3 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NPCM_I2CCST2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NPCM_I2CCST3 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I2C_VER 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*BANK0 regs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NPCM_I2CADDR3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define NPCM_I2CADDR7 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NPCM_I2CADDR4 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NPCM_I2CADDR8 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define NPCM_I2CADDR5 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define NPCM_I2CADDR9 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NPCM_I2CADDR6 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NPCM_I2CADDR10 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * npcm_i2caddr array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * The module supports having multiple own slave addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Since the addr regs are sprinkled all over the address space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * use this array to get the address or each register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define I2C_NUM_OWN_ADDR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) NPCM_I2CADDR9, NPCM_I2CADDR10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define NPCM_I2CCTL4 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NPCM_I2CCTL5 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NPCM_I2CSCLHT 0x1E /* SCL High Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* BANK 1 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NPCM_I2CPEC 0x16 /* PEC Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* NPCM_I2CST reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define NPCM_I2CST_XMIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define NPCM_I2CST_MASTER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NPCM_I2CST_NMATCH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define NPCM_I2CST_STASTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NPCM_I2CST_NEGACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NPCM_I2CST_BER BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define NPCM_I2CST_SDAST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define NPCM_I2CST_SLVSTP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* NPCM_I2CCST reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NPCM_I2CCST_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NPCM_I2CCST_BB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NPCM_I2CCST_MATCH BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NPCM_I2CCST_GCMATCH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NPCM_I2CCST_TSDA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define NPCM_I2CCST_TGSCL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NPCM_I2CCST_MATCHAF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define NPCM_I2CCST_ARPMATCH BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* NPCM_I2CCTL1 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define NPCM_I2CCTL1_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define NPCM_I2CCTL1_STOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define NPCM_I2CCTL1_INTEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define NPCM_I2CCTL1_EOBINTE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define NPCM_I2CCTL1_ACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NPCM_I2CCTL1_GCMEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NPCM_I2CCTL1_NMINTE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define NPCM_I2CCTL1_STASTRE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* RW1S fields (inside a RW reg): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NPCM_I2CCTL1_RWS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* npcm_i2caddr reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define NPCM_I2CADDR_A GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define NPCM_I2CADDR_SAEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* NPCM_I2CCTL2 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define I2CCTL2_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* NPCM_I2CCTL3 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define I2CCTL3_ARPMEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define I2CCTL3_IDL_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define I2CCTL3_400K_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define I2CCTL3_BNK_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define I2CCTL3_SDA_LVL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define I2CCTL3_SCL_LVL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* NPCM_I2CCST2 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define NPCM_I2CCST2_MATCHA1F BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define NPCM_I2CCST2_MATCHA2F BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define NPCM_I2CCST2_MATCHA3F BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define NPCM_I2CCST2_MATCHA4F BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define NPCM_I2CCST2_MATCHA5F BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define NPCM_I2CCST2_MATCHA6F BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define NPCM_I2CCST2_MATCHA7F BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define NPCM_I2CCST2_INTSTS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* NPCM_I2CCST3 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define NPCM_I2CCST3_MATCHA8F BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define NPCM_I2CCST3_MATCHA9F BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define NPCM_I2CCST3_MATCHA10F BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define NPCM_I2CCST3_EO_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* NPCM_I2CCTL4 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define I2CCTL4_HLDT GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define I2CCTL4_LVL_WE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* NPCM_I2CCTL5 reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define I2CCTL5_DBNCT GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* NPCM_I2CFIF_CTS reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* NPCM_I2CTXF_CTL reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define NPCM_I2CTXF_CTL_TX_THR GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* NPCM_I2CT_OUT reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define NPCM_I2CT_OUT_T_OUTIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define NPCM_I2CT_OUT_T_OUTST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* NPCM_I2CTXF_STS reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define NPCM_I2CTXF_STS_TX_BYTES GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define NPCM_I2CTXF_STS_TX_THST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* NPCM_I2CRXF_STS reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define NPCM_I2CRXF_STS_RX_BYTES GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define NPCM_I2CRXF_STS_RX_THST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* NPCM_I2CFIF_CTL reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* NPCM_I2CRXF_CTL reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define NPCM_I2CRXF_CTL_RX_THR GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define NPCM_I2CRXF_CTL_LAST_PEC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define I2C_HW_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* I2C_VER reg fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define I2C_VER_VERSION GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define I2C_VER_FIFO_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* stall/stuck timeout in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DEFAULT_STALL_COUNT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* SCLFRQ field position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SCLFRQ_0_TO_6 GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SCLFRQ_7_TO_8 GENMASK(8, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* supported clk settings. values in Hz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define I2C_FREQ_MIN_HZ 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Status of one I2C module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct npcm_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned char __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spinlock_t lock; /* IRQ synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct i2c_msg *msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int msgs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 apb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct i2c_bus_recovery_info rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) enum i2c_oper operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) enum i2c_mode master_or_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum i2c_state_ind stop_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 dest_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 *rd_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u16 rd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u16 rd_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 *wr_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 wr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u16 wr_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bool fifo_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u16 PEC_mask; /* PEC bit mask per slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bool PEC_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool read_block_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned long int_time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long bus_freq; /* in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 own_slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int slv_rd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int slv_rd_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int slv_wr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int slv_wr_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 slv_rd_buf[I2C_HW_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 slv_wr_buf[I2C_HW_FIFO_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dentry *debugfs; /* debugfs device directory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u64 ber_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u64 rec_succ_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u64 rec_fail_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u64 nack_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u64 timeout_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum i2c_bank bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (bank == I2C_BANK_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void npcm_i2c_init_params(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bus->stop_ind = I2C_NO_STATUS_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bus->rd_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bus->wr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bus->rd_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bus->wr_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) bus->read_block_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bus->int_time_stamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bus->PEC_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bus->PEC_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) iowrite8(data, bus->reg + NPCM_I2CSDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ioread8(bus->reg + NPCM_I2CSDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return !!(I2CCTL3_SCL_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return !!(I2CCTL3_SDA_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (bus->operation == I2C_READ_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return bus->rd_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (bus->operation == I2C_WRITE_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return bus->wr_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* quick protocol (just address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return bus->wr_size == 0 && bus->rd_size == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void npcm_i2c_disable(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 i2cctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* select bank 0 for I2C addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Slave addresses removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) iowrite8(0, bus->reg + npcm_i2caddr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Disable module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bus->state = I2C_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void npcm_i2c_enable(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* enable\disable end of busy (EOB) interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Clear EO_BUSY pending bit: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) val = ioread8(bus->reg + NPCM_I2CCST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val = val | NPCM_I2CCST3_EO_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) iowrite8(val, bus->reg + NPCM_I2CCST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) val &= ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val |= NPCM_I2CCTL1_EOBINTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val &= ~NPCM_I2CCTL1_EOBINTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u8 tx_fifo_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* check if TX FIFO is not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* check if TX FIFO status bit is set: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 rx_fifo_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* check if RX FIFO is not empty: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* check if rx fifo full status is set: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val = ioread8(bus->reg + NPCM_I2CTXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) val = val | NPCM_I2CTXF_STS_TX_THST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) val = ioread8(bus->reg + NPCM_I2CRXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val = val | NPCM_I2CRXF_STS_RX_THST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val &= ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val |= NPCM_I2CCTL1_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val &= ~NPCM_I2CCTL1_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val |= NPCM_I2CCTL1_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * override HW issue: I2C may fail to supply stop condition in Master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Need to delay at least 5 us from the last int, before issueing a stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) udelay(10); /* function called from interrupt, can't sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val |= NPCM_I2CCTL1_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!bus->fifo_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (bus->operation == I2C_READ_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val &= ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (stall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val |= NPCM_I2CCTL1_STASTRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val &= ~NPCM_I2CCTL1_STASTRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static inline void npcm_i2c_nack(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val |= NPCM_I2CCTL1_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 i2cctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* enable interrupt on slave match: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) i2cctl1 &= ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) i2cctl1 |= NPCM_I2CCTL1_NMINTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u8 addr, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u8 i2cctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 i2cctl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u8 sa_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (addr_type == I2C_GC_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) i2cctl1 |= NPCM_I2CCTL1_GCMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (addr_type == I2C_ARP_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) i2cctl3 |= I2CCTL3_ARPMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) i2cctl3 &= ~I2CCTL3_ARPMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (addr_type >= I2C_ARP_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* select bank 0 for address 3 to 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (addr_type > I2C_SLAVE_ADDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Set and enable the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) npcm_i2c_slave_int_enable(bus, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (addr_type > I2C_SLAVE_ADDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void npcm_i2c_reset(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Save I2CCTL1 relevant bits. It is being cleared when the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 i2cctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) npcm_i2c_disable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) npcm_i2c_enable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Restore NPCM_I2CCTL1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) i2cctl1 &= ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Clear BB (BUS BUSY) bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) iowrite8(0xFF, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Clear EOB bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) iowrite8(NPCM_I2CCST3_EO_BUSY, bus->reg + NPCM_I2CCST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Clear all fifo bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (bus->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) addr = bus->slave->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void npcm_i2c_callback(struct npcm_i2c *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) enum i2c_state_ind op_status, u16 info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct i2c_msg *msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int msgs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) msgs = bus->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) msgs_num = bus->msgs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * check that transaction was not timed-out, and msgs still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * holds a valid value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (completion_done(&bus->cmd_complete))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) switch (op_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case I2C_MASTER_DONE_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) bus->cmd_err = bus->msgs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case I2C_BLOCK_BYTES_ERR_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Master tx finished and all transmit bytes were sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (bus->msgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (msgs[0].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) msgs[0].len = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else if (msgs_num == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) msgs[1].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) msgs[1].len = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (completion_done(&bus->cmd_complete) == false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) complete(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case I2C_NACK_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* MASTER transmit got a NACK before tx all bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) bus->cmd_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (bus->master_or_slave == I2C_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) complete(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case I2C_BUS_ERR_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) bus->cmd_err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (bus->master_or_slave == I2C_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) complete(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case I2C_WAKE_UP_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* I2C wake up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) bus->operation = I2C_NO_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (bus->operation == I2C_WRITE_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ioread8(bus->reg + NPCM_I2CTXF_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (bus->operation == I2C_READ_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ioread8(bus->reg + NPCM_I2CRXF_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 size_free_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * Fill the FIFO, while the FIFO is not full and there are more bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) while (max_bytes-- && size_free_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (bus->wr_ind < bus->wr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) npcm_i2c_wr_byte(bus, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * npcm_i2c_set_fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * configure the FIFO before using it. If nread is -1 RX FIFO will not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * configured. same for nwrite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u8 rxf_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!bus->fifo_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* configure RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (nread > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* set LAST bit. if LAST is set next FIFO packet is nacked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (nread <= I2C_HW_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * if we are about to read the first byte in blk rd mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * don't NACK it. If slave returns zero size HW can't NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * it immidiattly, it will read extra byte and then NACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (bus->rd_ind == 0 && bus->read_block_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* set fifo to read one byte, no last: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) rxf_ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* set fifo size: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* configure TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (nwrite > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (nwrite > I2C_HW_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* data to send is more then FIFO size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) while (bytes_in_fifo--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) data = npcm_i2c_rd_byte(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (bus->rd_ind < bus->rd_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) bus->rd_buf[bus->rd_ind++] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Clear NEGACK, STASTR and BER bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) iowrite8(val, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static void npcm_i2c_master_abort(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Only current master is allowed to issue a stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!npcm_i2c_is_master(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) npcm_i2c_eob_int(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) npcm_i2c_clear_master_status(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u8 slave_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* select bank 0 for address 3 to 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (addr_type > I2C_SLAVE_ADDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (addr_type > I2C_SLAVE_ADDR2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return slave_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Set the enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) slave_add |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) iowrite8(0, bus->reg + npcm_i2caddr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Fill the FIFO, while the FIFO is not full and there are more bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (bus->slv_wr_size <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) bus->slv_wr_ind++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) bus->slv_wr_size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) while (bytes_in_fifo--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) data = npcm_i2c_rd_byte(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bus->slv_rd_buf[bus->slv_rd_ind] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) bus->slv_rd_ind++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* 1st byte is length in block protocol: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (bus->slv_rd_ind == 1 && bus->read_block_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bus->slv_rd_size = data + bus->PEC_use + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int ret = bus->slv_wr_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* fill a cyclic buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) for (i = 0; i < I2C_HW_FIFO_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bus->slv_wr_buf[ind] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) bus->slv_wr_size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return I2C_HW_FIFO_SIZE - ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for (i = 0; i < bus->slv_rd_ind; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &bus->slv_rd_buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * once we send bytes up, need to reset the counter of the wr buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * got data from master (new offset in device), ignore wr fifo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (bus->slv_rd_ind) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) bus->slv_wr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) bus->slv_wr_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) bus->slv_rd_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) bus->slv_rd_size = bus->adap.quirks->max_read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u8 *read_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) bus->state = I2C_OPER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) bus->slv_rd_size = nread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bus->slv_rd_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 *write_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (nwrite == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) bus->state = I2C_OPER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* get the next buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) npcm_i2c_slave_get_wr_buf(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) npcm_i2c_write_fifo_slave(bus, nwrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * npcm_i2c_slave_wr_buf_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * currently slave IF only supports single byte operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * in order to utilyze the npcm HW FIFO, the driver will ask for 16 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * at a time, pack them in buffer, and then transmit them all together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * to the FIFO and onward to the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * NACK on read will be once reached to bus->adap->quirks->max_read_len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * sending a NACK wherever the backend requests for it is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * the next two functions allow reading to local buffer before writing it all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * to the HW FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) int left_in_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ioread8(bus->reg + NPCM_I2CTXF_STS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* fifo already full: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (left_in_fifo >= I2C_HW_FIFO_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* update the wr fifo index back to the untransmitted bytes: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (bus->slv_wr_ind < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Slave got an address match with direction bit 1 so it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * transmit data. Write till the master will NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) bus->slv_wr_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * Slave got an address match with direction bit 0 so it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * receive data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * this module does not support saying no to bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * it will always ACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) bus->stop_ind = I2C_SLAVE_RCV_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) npcm_i2c_slave_send_rd_buf(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) bus->slv_rd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Slave: A NACK has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (NPCM_I2CST_NEGACK & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) bus->stop_ind = I2C_NACK_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) npcm_i2c_slave_wr_buf_sync(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (bus->fifo_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* In slave write, NACK is OK, otherwise it is a problem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) bus->stop_ind = I2C_NO_STATUS_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) bus->operation = I2C_NO_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) bus->own_slave_addr = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * Slave has to wait for STOP to decide this is the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * of the transaction. tx is not yet considered as done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Slave mode: a Bus Error (BER) has been identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (NPCM_I2CST_BER & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Check whether bus arbitration or Start or Stop during data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * xfer bus arbitration problem should not result in recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bus->stop_ind = I2C_BUS_ERR_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* wait for bus busy before clear fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * in BER case we might get 2 interrupts: one for slave one for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * master ( for a channel which is master\slave switching)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (completion_done(&bus->cmd_complete) == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) complete(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) bus->own_slave_addr = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* A Slave Stop Condition has been identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (NPCM_I2CST_SLVSTP & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) bus->stop_ind = I2C_SLAVE_DONE_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (bus->operation == I2C_READ_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* if the buffer is empty nothing will be sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) npcm_i2c_slave_send_rd_buf(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* Slave done transmitting or receiving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bus->stop_ind = I2C_NO_STATUS_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Note, just because we got here, it doesn't mean we through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * away the wr buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * we keep it until the next received offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) bus->operation = I2C_NO_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) bus->own_slave_addr = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (bus->fifo_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* restart condition occurred and Rx-FIFO was not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) bus->stop_ind = I2C_SLAVE_RESTART_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (bus->operation == I2C_READ_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) NPCM_I2CFIF_CTS_RXF_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) npcm_i2c_slave_rd_wr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* A Slave Address Match has been identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (NPCM_I2CST_NMATCH & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u8 info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Address match automatically implies slave mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (NPCM_I2CST_XMIT & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (bus->own_slave_addr == 0xFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Check which type of address match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) val = ioread8(bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (NPCM_I2CCST_MATCH & val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) enum i2c_addr eaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 i2ccst2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u8 i2ccst3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * the i2c module can response to 10 own SA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * check which one was addressed by the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * repond to the first one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) addr = ((i2ccst3 & 0x07) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) (i2ccst2 & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) info = ffs(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) eaddr = (enum i2c_addr)info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) addr = npcm_i2c_get_slave_addr(bus, eaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) addr &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) bus->own_slave_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (bus->PEC_mask & BIT(info))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) bus->PEC_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) bus->PEC_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (NPCM_I2CCST_GCMATCH & val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) bus->own_slave_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (NPCM_I2CCST_ARPMATCH & val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) bus->own_slave_addr = 0x61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * Slave match can happen in two options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * 1. Start, SA, read (slave read without further ado)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * 2. Start, SA, read, data, restart, SA, read, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * (slave read in fragmented mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * 3. Start, SA, write, data, restart, SA, read, ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * (regular write-read mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if ((bus->state == I2C_OPER_STARTED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) bus->operation == I2C_READ_OPER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) bus->stop_ind == I2C_SLAVE_RCV_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* slave tx after slave rx w/o STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) bus->stop_ind = I2C_SLAVE_RESTART_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (NPCM_I2CST_XMIT & i2cst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) bus->stop_ind = I2C_SLAVE_XMIT_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) bus->stop_ind = I2C_SLAVE_RCV_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) bus->state = I2C_SLAVE_MATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) npcm_i2c_slave_rd_wr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* Slave SDA status is set - tx or rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if ((NPCM_I2CST_SDAST & i2cst) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) (bus->fifo_use &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) npcm_i2c_slave_rd_wr(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) } /* SDAST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int npcm_i2c_reg_slave(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) bus->slave = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (client->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) spin_lock_irqsave(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) npcm_i2c_init_params(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) bus->slv_rd_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) bus->slv_wr_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) bus->slv_rd_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) bus->slv_wr_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (client->flags & I2C_CLIENT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) bus->PEC_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) client->addr, bus->PEC_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) npcm_i2c_clear_fifo_int(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) npcm_i2c_slave_int_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) spin_unlock_irqrestore(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static int npcm_i2c_unreg_slave(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct npcm_i2c *bus = client->adapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) spin_lock_irqsave(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!bus->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) spin_unlock_irqrestore(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) npcm_i2c_slave_int_enable(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) npcm_i2c_remove_slave_addr(bus, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) bus->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) spin_unlock_irqrestore(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #endif /* CONFIG_I2C_SLAVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int rcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int fifo_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) fifo_bytes = npcm_i2c_fifo_usage(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) rcount = bus->rd_size - bus->rd_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * In order not to change the RX_TRH during transaction (we found that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * this might be problematic if it takes too much time to read the FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * we read the data in the following way. If the number of bytes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * and in the next int we read rest of the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) fifo_bytes = rcount - I2C_HW_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (rcount <= fifo_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* last bytes are about to be read - end of tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) bus->state = I2C_STOP_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) bus->stop_ind = ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) npcm_i2c_eob_int(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Stop should be set before reading last byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) npcm_i2c_read_fifo(bus, fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) npcm_i2c_read_fifo(bus, fifo_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) rcount = bus->rd_size - bus->rd_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) npcm_i2c_set_fifo(bus, rcount, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) u16 wcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (bus->fifo_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Master write operation - last byte handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (bus->wr_ind == bus->wr_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * No more bytes to send (to add to the FIFO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * however the FIFO is not empty yet. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * still in the middle of tx. Currently there's nothing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * to do except for waiting to the end of the tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * We will get an int when the FIFO will get empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (bus->rd_size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* all bytes have been written, in wr only operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) npcm_i2c_eob_int(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) bus->state = I2C_STOP_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) bus->stop_ind = I2C_MASTER_DONE_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Clear SDA Status bit (by writing dummy byte) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) npcm_i2c_wr_byte(bus, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* last write-byte written on previous int - restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) npcm_i2c_set_fifo(bus, bus->rd_size, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Generate repeated start upon next write to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) npcm_i2c_master_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * Receiving one byte only - stall after successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * completion of send address byte. If we NACK here, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * slave doesn't ACK the address, we might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * unintentionally NACK the next multi-byte read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (bus->rd_size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) npcm_i2c_stall_after_start(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Next int will occur on read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* send the slave address in read direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* write next byte not last byte and not slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (!bus->fifo_use || bus->wr_size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) wcount = bus->wr_size - bus->wr_ind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) npcm_i2c_set_fifo(bus, -1, wcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (wcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) npcm_i2c_write_to_fifo_master(bus, wcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) u16 block_extra_bytes_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* added bytes to the packet: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * Perform master read, distinguishing between last byte and the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * the bytes. The last byte should be read when the clock is stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (bus->rd_ind == 0) { /* first byte handling: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (bus->read_block_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* first byte in block protocol is the size: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data = npcm_i2c_rd_byte(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) bus->rd_size = data + block_extra_bytes_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) bus->rd_buf[bus->rd_ind++] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* clear RX FIFO interrupt status: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (bus->fifo_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) data = data | NPCM_I2CFIF_CTS_RXF_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) npcm_i2c_stall_after_start(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) npcm_i2c_master_fifo_read(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (bus->rd_size == block_extra_bytes_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) bus->read_block_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) bus->state = I2C_STOP_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) npcm_i2c_eob_int(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) npcm_i2c_master_fifo_read(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) npcm_i2c_nack(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) bus->stop_ind = I2C_BUS_ERR_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* A NACK has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (bus->nack_cnt < ULLONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) bus->nack_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (bus->fifo_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * if there are still untransmitted bytes in TX FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * reduce them from wr_ind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (bus->operation == I2C_WRITE_OPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) bus->wr_ind -= npcm_i2c_fifo_usage(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* clear the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* In master write operation, got unexpected NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) bus->stop_ind = I2C_NACK_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Only current master is allowed to issue Stop Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (npcm_i2c_is_master(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* stopping in the middle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) npcm_i2c_eob_int(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) * The bus is released from stall only after the SW clears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * NEGACK bit. Then a Stop condition is sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) npcm_i2c_clear_master_status(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) !(val & NPCM_I2CCST_BUSY), 10, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * In Master mode, NACK should be cleared only after STOP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * In such case, the bus is released from stall only after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * software clears NACK bit. Then a Stop condition is sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Master mode: a Bus Error has been identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (bus->ber_cnt < ULLONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) bus->ber_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) bus->stop_ind = I2C_BUS_ERR_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (npcm_i2c_is_master(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) npcm_i2c_master_abort(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) npcm_i2c_clear_master_status(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Clear BB (BUS BUSY) bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) bus->cmd_err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* EOB: a master End Of Busy (meaning STOP completed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) npcm_i2c_eob_int(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* Address sent and requested stall occurred (Master mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (npcm_i2c_is_quick(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) bus->state = I2C_STOP_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) bus->stop_ind = I2C_MASTER_DONE_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) npcm_i2c_eob_int(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) } else if ((bus->rd_size == 1) && !bus->read_block_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * Receiving one byte only - set NACK after ensuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * slave ACKed the address byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) npcm_i2c_nack(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* Reset stall-after-address-byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) npcm_i2c_stall_after_start(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* Clear stall only after setting STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* SDA status is set - TX or RX, master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u8 fif_cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (!npcm_i2c_is_master(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (bus->state == I2C_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) bus->stop_ind = I2C_WAKE_UP_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (npcm_i2c_is_quick(bus) || bus->read_block_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * Need to stall after successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * completion of sending address byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) npcm_i2c_stall_after_start(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) npcm_i2c_stall_after_start(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * Receiving one byte only - stall after successful completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * of sending address byte If we NACK here, and slave doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * ACK the address, we might unintentionally NACK the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * multi-byte read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (bus->wr_size == 0 && bus->rd_size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) npcm_i2c_stall_after_start(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Initiate I2C master tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* select bank 1 for FIFO regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* clear FIFO and relevant status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* re-enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * Configure the FIFO threshold:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) * according to the needed # of bytes to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * Note: due to HW limitation can't config the rx fifo before it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * got and ACK on the restart. LAST bit will not be reset unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) * RX completed. It will stay set on the next tx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (bus->wr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) npcm_i2c_set_fifo(bus, -1, bus->wr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) npcm_i2c_set_fifo(bus, bus->rd_size, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) bus->state = I2C_OPER_STARTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (npcm_i2c_is_quick(bus) || bus->wr_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) npcm_i2c_wr_byte(bus, bus->dest_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* SDA interrupt, after start\restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (NPCM_I2CST_XMIT & i2cst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) npcm_i2c_irq_master_handler_write(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) npcm_i2c_irq_master_handler_read(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) u8 i2cst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) int ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) i2cst = ioread8(bus->reg + NPCM_I2CST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) npcm_i2c_irq_handle_nmatch(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* A NACK has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) npcm_i2c_irq_handle_nack(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* Master mode: a Bus Error has been identified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) npcm_i2c_irq_handle_ber(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* EOB: a master End Of Busy (meaning STOP completed) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ioread8(bus->reg + NPCM_I2CCST3)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) npcm_i2c_irq_handle_eob(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* Address sent and requested stall occurred (Master mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) npcm_i2c_irq_handle_stall_after_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* SDA status is set - TX or RX, master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) (bus->fifo_use &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) npcm_i2c_irq_handle_sda(bus, i2cst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* recovery using TGCLK functionality of the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u8 fif_cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) bool done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int status = -ENOTRECOVERABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* Allow 3 bytes (27 toggles) to be read from the slave: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) int iter = 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) dev_dbg(bus->dev, "bus%d recovery skipped, bus not stuck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) bus->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) npcm_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) npcm_i2c_int_enable(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) npcm_i2c_disable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) npcm_i2c_enable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) npcm_i2c_clear_tx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) npcm_i2c_clear_rx_fifo(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) npcm_i2c_stall_after_start(bus, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* select bank 1 for FIFO regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* clear FIFO and relevant status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) npcm_i2c_set_fifo(bus, -1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* Repeat the following sequence until SDA is released */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /* Issue a single SCL toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* If SDA line is inactive (high), stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (npcm_i2c_get_SDA(_adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) } while (!done && iter--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* If SDA line is released: send start-addr-stop, to re-sync. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (npcm_i2c_get_SDA(_adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Send an address byte in write direction: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) npcm_i2c_wr_byte(bus, bus->dest_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) npcm_i2c_master_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* Wait until START condition is sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) 20, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* If START condition was sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (npcm_i2c_is_master(bus) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) npcm_i2c_master_stop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) usleep_range(200, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) npcm_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) npcm_i2c_int_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) status = -ENOTRECOVERABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (bus->rec_fail_cnt < ULLONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) bus->rec_fail_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (bus->rec_succ_cnt < ULLONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) bus->rec_succ_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* recovery using bit banging functionality of the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) rinfo->recover_bus = npcm_i2c_recovery_tgclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * npcm i2c HW allows direct reading of SCL and SDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * However, it does not support setting SCL and SDA directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * The recovery function can togle SCL when SDA is low (but not set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * Getter functions used internally, and can be used externaly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) rinfo->get_scl = npcm_i2c_get_SCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) rinfo->get_sda = npcm_i2c_get_SDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) _adap->bus_recovery_info = rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* SCLFRQ min/max field values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define SCLFRQ_MIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define SCLFRQ_MAX 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * npcm_i2c_init_clk: init HW timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * NPCM7XX i2c module timing parameters are depenent on module core clk (APB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * and bus frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * 400kHz bus requires assymetric HT and LT. A different equation is recomended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * by the HW designer, given core clock range (equations in comments below).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) u32 k1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) u32 k2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) u8 dbnct = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u32 sclfrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) u8 hldt = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) u8 fast_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) u32 src_clk_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 bus_freq_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) src_clk_khz = bus->apb_clk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) bus_freq_khz = bus_freq_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) bus->bus_freq = bus_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* 100KHz and below: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) sclfrq = src_clk_khz / (bus_freq_khz * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (src_clk_khz >= 40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) hldt = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) else if (src_clk_khz >= 12500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) hldt = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) hldt = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* 400KHz: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) sclfrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) fast_mode = I2CCTL3_400K_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (src_clk_khz < 7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* 400KHZ cannot be supported for core clock < 7.5MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) else if (src_clk_khz >= 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) k1 = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) k2 = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hldt = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) dbnct = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* Master or Slave with frequency > 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) else if (src_clk_khz > 25000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) hldt = clk_coef(src_clk_khz, 300) + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) k1 = clk_coef(src_clk_khz, 1600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) k2 = clk_coef(src_clk_khz, 900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* 1MHz: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) sclfrq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) fast_mode = I2CCTL3_400K_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* 1MHZ cannot be supported for core clock < 24 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (src_clk_khz < 24000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) k1 = clk_coef(src_clk_khz, 620);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) k2 = clk_coef(src_clk_khz, 380);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* Core clk > 40 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (src_clk_khz > 40000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * Set HLDT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * SDA hold time: (HLDT-7) * T(CLK) >= 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) hldt = clk_coef(src_clk_khz, 120) + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) hldt = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dbnct = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* Frequency larger than 1 MHz is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) k1 = round_up(k1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) k2 = round_up(k2 + 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) bus->reg + NPCM_I2CCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* bits [8:7] are in I2CCTL3 reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) bus->reg + NPCM_I2CCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * Set SCL Low/High Time:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* Return to Bank 1, and stay there by default: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) u32 bus_freq_hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* Check whether module already enabled or frequency is out of bounds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) npcm_i2c_disable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Configure FIFO mode : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) bus->fifo_use = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) npcm_i2c_select_bank(bus, I2C_BANK_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) val |= NPCM_I2CFIF_CTL_FIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) bus->fifo_use = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* Configure I2C module clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ret = npcm_i2c_init_clk(bus, bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* Enable module (before configuring CTL1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) npcm_i2c_enable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) val = ioread8(bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) iowrite8(val, bus->reg + NPCM_I2CCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) npcm_i2c_int_enable(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) npcm_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) u32 clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* Initialize the internal data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) bus->state = I2C_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) bus->int_time_stamp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) bus->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ret = device_property_read_u32(&pdev->dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) &clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) dev_info(&pdev->dev, "Could not read clock-frequency property");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct npcm_i2c *bus = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (npcm_i2c_is_master(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) bus->master_or_slave = I2C_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (bus->master_or_slave == I2C_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) bus->int_time_stamp = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (!npcm_i2c_int_master_handler(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (bus->slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) bus->master_or_slave = I2C_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return npcm_i2c_int_slave_handler(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) u8 slave_addr, u16 nwrite, u16 nread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) u8 *write_data, u8 *read_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) bool use_PEC, bool use_read_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (bus->state != I2C_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) bus->cmd_err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) bus->dest_addr = slave_addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) bus->wr_buf = write_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) bus->wr_size = nwrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) bus->wr_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) bus->rd_buf = read_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) bus->rd_size = nread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) bus->rd_ind = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) bus->PEC_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (nread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) bus->PEC_use = use_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) bus->read_block_use = use_read_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (nread && !nwrite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) bus->operation = I2C_READ_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) bus->operation = I2C_WRITE_OPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) if (bus->fifo_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) u8 i2cfif_cts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) npcm_i2c_select_bank(bus, I2C_BANK_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* clear FIFO and relevant status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) npcm_i2c_stall_after_start(bus, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) npcm_i2c_master_start(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) struct i2c_msg *msg0, *msg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) u16 nwrite, nread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) u8 *write_data, *read_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) u8 slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) bool read_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) bool read_PEC = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) u8 bus_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) unsigned long timeout_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (bus->state == I2C_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) dev_err(bus->dev, "I2C%d module is disabled", bus->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) msg0 = &msgs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) slave_addr = msg0->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (msg0->flags & I2C_M_RD) { /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) nwrite = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) write_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) read_data = msg0->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (msg0->flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) nread = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) read_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (msg0->flags & I2C_CLIENT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) read_PEC = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) nread = msg0->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) } else { /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) nwrite = msg0->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) write_data = msg0->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) nread = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) read_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) msg1 = &msgs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) read_data = msg1->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (msg1->flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) nread = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) read_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (msg1->flags & I2C_CLIENT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) read_PEC = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) nread = msg1->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) read_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * Adaptive TimeOut: estimated time in usec + 100% margin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * 2: double the timeout for clock stretching case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) * 9: bits per transaction (including the ack/nack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) timeout = max(msecs_to_jiffies(35), usecs_to_jiffies(timeout_usec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) time_left = jiffies + msecs_to_jiffies(DEFAULT_STALL_COUNT) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * we must clear slave address immediately when the bus is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) * busy, so we spinlock it, but we don't keep the lock for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) * entire while since it is too long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) spin_lock_irqsave(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) if (!bus_busy && bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) iowrite8((bus->slave->addr & 0x7F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) bus->reg + NPCM_I2CADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) spin_unlock_irqrestore(&bus->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) } while (time_is_after_jiffies(time_left) && bus_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (bus_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) npcm_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) npcm_i2c_init_params(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) bus->dest_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) bus->msgs = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) bus->msgs_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) bus->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) bus->read_block_use = read_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) reinit_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (!npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) write_data, read_data, read_PEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) read_block))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (ret != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) time_left = wait_for_completion_timeout(&bus->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (bus->timeout_cnt < ULLONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) bus->timeout_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (bus->master_or_slave == I2C_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) bus->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) bus->state = I2C_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ret = bus->cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* if there was BER, check if need to recover the bus: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (bus->cmd_err == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ret = i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * After any type of error, check if LAST bit is still set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * due to a HW issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) * It cannot be cleared without resetting the module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (bus->cmd_err &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) npcm_i2c_reset(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* reenable slave if it was enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (bus->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) bus->reg + NPCM_I2CADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) return bus->cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) I2C_FUNC_SMBUS_EMUL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) I2C_FUNC_SMBUS_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) I2C_FUNC_SMBUS_PEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) I2C_FUNC_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static const struct i2c_adapter_quirks npcm_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .max_read_len = 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .max_write_len = 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static const struct i2c_algorithm npcm_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .master_xfer = npcm_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .functionality = npcm_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #if IS_ENABLED(CONFIG_I2C_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .reg_slave = npcm_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .unreg_slave = npcm_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* i2c debugfs directory: used to keep health monitor of i2c devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static struct dentry *npcm_i2c_debugfs_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static void npcm_i2c_init_debugfs(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct npcm_i2c *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct dentry *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) if (!npcm_i2c_debugfs_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) if (IS_ERR_OR_NULL(d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) bus->debugfs = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static int npcm_i2c_probe_bus(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct npcm_i2c *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct clk *i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static struct regmap *gcr_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static struct regmap *clk_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) bus->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /* core clk must be acquired to calculate module timing settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) i2c_clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (IS_ERR(i2c_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) return PTR_ERR(i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) bus->apb_clk = clk_get_rate(i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (IS_ERR(gcr_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) return PTR_ERR(gcr_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (IS_ERR(clk_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return PTR_ERR(clk_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) bus->reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (IS_ERR(bus->reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return PTR_ERR(bus->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) spin_lock_init(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) init_completion(&bus->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) adap = &bus->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) adap->timeout = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) adap->algo = &npcm_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) adap->quirks = &npcm_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) adap->algo_data = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) dev_name(bus->dev), bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ret = __npcm_i2c_init(bus, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) npcm_i2c_recovery_init(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) i2c_set_adapdata(adap, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) bus->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ret = i2c_add_numbered_adapter(&bus->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) npcm_i2c_init_debugfs(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static int npcm_i2c_remove_bus(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) unsigned long lock_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) struct npcm_i2c *bus = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) debugfs_remove_recursive(bus->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) spin_lock_irqsave(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) npcm_i2c_disable(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) spin_unlock_irqrestore(&bus->lock, lock_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) i2c_del_adapter(&bus->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static const struct of_device_id npcm_i2c_bus_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) { .compatible = "nuvoton,npcm750-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static struct platform_driver npcm_i2c_bus_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .probe = npcm_i2c_probe_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .remove = npcm_i2c_remove_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .name = "nuvoton-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .of_match_table = npcm_i2c_bus_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static int __init npcm_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) platform_driver_register(&npcm_i2c_bus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) module_init(npcm_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static void __exit npcm_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) platform_driver_unregister(&npcm_i2c_bus_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) debugfs_remove_recursive(npcm_i2c_debugfs_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) module_exit(npcm_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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