^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * I2C master mode controller driver, used in Nomadik 8815
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * and Ux500 platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Sachin Verma <sachin.verma@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRIVER_NAME "nmk-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* I2C Controller register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_CR (0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_SCR (0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_HSMCR (0x008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_MCR (0x00C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_TFR (0x010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_SR (0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_RFR (0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_TFTR (0x01C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_RFTR (0x020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_DMAR (0x024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_BRCR (0x028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_IMSCR (0x02C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_RISR (0x030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_MISR (0x034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_ICR (0x038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_CR_OM (0x3 << 1) /* Operating mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_CR_SM (0x3 << 4) /* Speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_CR_FON (0x3 << 13) /* Filtering on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Master controller (MCR) register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_MCR_OP (0x1 << 0) /* Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_MCR_SB (0x1 << 11) /* Extended address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_MCR_AM (0x3 << 12) /* Address type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Status register (SR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_SR_OP (0x3 << 0) /* Operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_SR_STATUS (0x3 << 2) /* controller status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Interrupt mask set/clear (IMSCR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_IT_TXFE (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_IT_TXFNE (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_IT_TXFF (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2C_IT_TXFOVR (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2C_IT_RXFE (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2C_IT_RXFNF (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C_IT_RXFF (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C_IT_RFSR (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2C_IT_RFSE (0x1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2C_IT_WTSR (0x1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2C_IT_MTD (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2C_IT_STD (0x1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2C_IT_MAL (0x1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2C_IT_BERR (0x1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2C_IT_MTDWS (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* some bits in ICR are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2C_CLEAR_ALL_INTS 0x131f007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* first three msb bits are reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRQ_MASK(mask) (mask & 0x1fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* maximum threshold value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX_I2C_FIFO_THRESHOLD 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum i2c_freq_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * struct i2c_vendor_data - per-vendor variations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @has_mtdws: variant has the MTDWS bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @fifodepth: variant FIFO depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_vendor_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool has_mtdws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 fifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum i2c_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) I2C_NOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) I2C_ON_GOING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) I2C_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) I2C_ABORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum i2c_operation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) I2C_NO_OPERATION = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) I2C_WRITE = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) I2C_READ = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * struct i2c_nmk_client - client specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @slave_adr: 7-bit slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @count: no. bytes to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @buffer: client data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @xfer_bytes: bytes transferred till now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @operation: current I2C operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct i2c_nmk_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned short slave_adr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned char *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long xfer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum i2c_operation operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * struct nmk_i2c_dev - private data structure of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @vendor: vendor data for this variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @adev: parent amba device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @adap: corresponding I2C adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @irq: interrupt line for the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @virtbase: virtual io memory area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @clk: hardware i2c block clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @cli: holder of client specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @clk_freq: clock frequency for the operation mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @tft: Tx FIFO Threshold in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @rft: Rx FIFO Threshold in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @timeout Slave response timeout (ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @sm: speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @stop: stop condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @xfer_complete: acknowledge completion for a I2C message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @result: controller propogated result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct nmk_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i2c_vendor_data *vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct amba_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct i2c_nmk_client cli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char tft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned char rft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum i2c_freq_mode sm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct completion xfer_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* controller's abort causes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char *abort_causes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "no ack received after address transmission",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "no ack received during data phase",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "ack received after xmission of master code",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "master lost arbitration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "slave restarts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "slave reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "overflow, maxsize is 2047 bytes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void i2c_set_bit(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(readl(reg) | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(readl(reg) & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * flush_i2c_fifo() - This function flushes the I2C FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * This function flushes the I2C Tx and Rx FIFOs. It returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 0 on successful flushing of FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LOOP_ATTEMPTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * flush the transmit and receive FIFO. The flushing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * operation takes several cycles before to be completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * On the completion, the I2C internal logic clears these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * bits, until then no one must access Tx, Rx FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * should poll on these bits waiting for the completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < LOOP_ATTEMPTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) timeout = jiffies + dev->adap.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) while (!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((readl(dev->virtbase + I2C_CR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (I2C_CR_FTX | I2C_CR_FRX)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(&dev->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "flushing operation timed out giving up after %d attempts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LOOP_ATTEMPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * disable_all_interrupts() - Disable all interrupts of this I2c Bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void disable_all_interrupts(struct nmk_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 mask = IRQ_MASK(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(mask, dev->virtbase + I2C_IMSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * clear_all_interrupts() - Clear all interrupts of I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void clear_all_interrupts(struct nmk_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(mask, dev->virtbase + I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * init_hw() - initialize the I2C hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int init_hw(struct nmk_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) stat = flush_i2c_fifo(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* disable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) disable_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clear_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev->cli.operation = I2C_NO_OPERATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* enable peripheral, master mode operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * load_i2c_mcr_reg() - load the MCR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @dev: private data of controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @flags: message flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned short slave_adr_3msb_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (unlikely(flags & I2C_M_TEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* 10-bit address transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Get the top 3 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * EA10 represents extended address in MCR. This includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * the extension (MSB bits) of the 7 bit address loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * in A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* 7-bit address transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* start byte procedure not applied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* check the operation, master read/write? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (dev->cli.operation == I2C_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* stop or repeated start? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (dev->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * setup_i2c_controller() - setup the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @dev: private data of controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void setup_i2c_controller(struct nmk_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 brcr1, brcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 i2c_clk, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 slsu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(0x0, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(0x0, dev->virtbase + I2C_HSMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(0x0, dev->virtbase + I2C_TFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel(0x0, dev->virtbase + I2C_RFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writel(0x0, dev->virtbase + I2C_DMAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) i2c_clk = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * set the slsu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * slsu defines the data setup time after SCL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * stretching in terms of i2c clk cycles + 1 (zero means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * "wait one cycle"), the needed setup time for the three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * modes are 250ns, 100ns, 10ns respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * As the time for one cycle T in nanoseconds is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * T = (1/f) * 1000000000 =>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * slsu = cycles / (1000000000 / f) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (dev->sm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case I2C_FREQ_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case I2C_FREQ_MODE_FAST_PLUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) slsu = DIV_ROUND_UP(100, ns); /* Fast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case I2C_FREQ_MODE_HIGH_SPEED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) slsu = DIV_ROUND_UP(10, ns); /* High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case I2C_FREQ_MODE_STANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) slsu = DIV_ROUND_UP(250, ns); /* Standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) slsu += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(slsu << 16, dev->virtbase + I2C_SCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * The spec says, in case of std. mode the divider is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * 2 whereas it is 3 for fast and fastplus mode of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * operation. TODO - high speed support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * generate the mask for baud rate counters. The controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * has two baud rate counters. One is used for High speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * operation, and the other is for std, fast mode, fast mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * plus operation. Currently we do not supprt high speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * so set brcr1 to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) brcr1 = 0 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* set the baud rate counter register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * set the speed mode. Currently we support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * only standard and fast mode of operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * TODO - support for fast mode plus (up to 1Mb/s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * and high speed (up to 3.4 Mb/s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (dev->sm > I2C_FREQ_MODE_FAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&dev->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) "do not support this mode defaulting to std. mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(I2C_FREQ_MODE_STANDARD << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel(dev->sm << 4, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* set the Tx and Rx FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel(dev->tft, dev->virtbase + I2C_TFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) writel(dev->rft, dev->virtbase + I2C_RFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * read_i2c() - Read from I2C client device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @flags: message flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * This function reads from i2c client device when controller is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * master mode. There is a completion timeout. If there is no transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * before timeout error is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 mcr, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mcr = load_i2c_mcr_reg(dev, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) writel(mcr, dev->virtbase + I2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* load the current CR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* enable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) init_completion(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* enable interrupts by setting the mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) I2C_IT_MAL | I2C_IT_BERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dev->stop || !dev->vendor->has_mtdws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) irq_mask |= I2C_IT_MTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) irq_mask |= I2C_IT_MTDWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev->virtbase + I2C_IMSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) timeout = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) &dev->xfer_complete, dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Controller timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev->cli.slave_adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (count = (no_bytes - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (count > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (dev->cli.count != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* write to the Tx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writeb(*dev->cli.buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev->virtbase + I2C_TFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev->cli.buffer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev->cli.count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev->cli.xfer_bytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * write_i2c() - Write data to I2C client.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @dev: private data of I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @flags: message flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * This function writes data to I2C client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 mcr, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mcr = load_i2c_mcr_reg(dev, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(mcr, dev->virtbase + I2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* load the current CR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* enable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) init_completion(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* enable interrupts by settings the masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Fill the TX FIFO with transmit data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (dev->cli.count != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) irq_mask |= I2C_IT_TXFNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * check if we want to transfer a single or multiple bytes, if so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * set the MTDWS bit (Master Transaction Done Without Stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * to start repeated start operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (dev->stop || !dev->vendor->has_mtdws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) irq_mask |= I2C_IT_MTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) irq_mask |= I2C_IT_MTDWS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev->virtbase + I2C_IMSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) timeout = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) &dev->xfer_complete, dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Controller timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev->cli.slave_adr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * nmk_i2c_xfer_one() - transmit a single I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * @dev: device with a message encoded into it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * @flags: message flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev->cli.operation = I2C_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) status = read_i2c(dev, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev->cli.operation = I2C_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) status = write_i2c(dev, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (status || (dev->result)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 i2c_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) i2c_sr = readl(dev->virtbase + I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Check if the controller I2C operation status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * is set to ABORT(11b).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (((i2c_sr >> 2) & 0x3) == 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* get the abort cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cause = (i2c_sr >> 4) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(&dev->adev->dev, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) cause >= ARRAY_SIZE(abort_causes) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) "unknown reason" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) abort_causes[cause]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) (void) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) status = status ? status : dev->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * nmk_i2c_xfer() - I2C transfer function used by kernel framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @i2c_adap: Adapter pointer to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @msgs: Pointer to data to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @num_msgs: Number of messages to be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * This is the function called by the generic kernel i2c_transfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * or i2c_smbus...() API calls. Note that this code is protected by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * semaphore set in the kernel i2c_transfer() function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * NOTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * READ TRANSFER : We impose a restriction of the first message to be the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * index message for any read transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * - a no index is coded as '0',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * - 2byte big endian index is coded as '3'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * !!! msg[0].buf holds the actual index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * This is compatible with generic messages of smbus emulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * that send a one byte index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * eg. a I2C transation to read 2 bytes from index 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * msg[0].flags = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * msg[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * msg[0].buf = &idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * msg[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * msg[1].buf = rd_buff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * i2c_transfer(adap, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * If you want to emulate an SMBUS write transaction put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * index as first byte(or first and second) in the payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * eg. a I2C transation to write 2 bytes from index 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * wr_buff[0] = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * wr_buff[1] = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * wr_buff[2] = 0x46;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * msg[0].flags = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * msg[0].len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * msg[0].buf = wr_buff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * i2c_transfer(adap, msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * To read or write a block of data (multiple bytes) using SMBUS emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * please use the i2c_smbus_read_i2c_block_data()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * or i2c_smbus_write_i2c_block_data() API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct i2c_msg msgs[], int num_msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pm_runtime_get_sync(&dev->adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Attempt three times to send the message queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) for (j = 0; j < 3; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* setup the i2c controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) setup_i2c_controller(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < num_msgs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev->cli.slave_adr = msgs[i].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev->cli.buffer = msgs[i].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev->cli.count = msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) status = nmk_i2c_xfer_one(dev, msgs[i].flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pm_runtime_put_sync(&dev->adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* return the no. messages processed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * disable_interrupts() - disable the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @dev: private data of controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) irq = IRQ_MASK(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dev->virtbase + I2C_IMSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * i2c_irq_handler() - interrupt routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * @irq: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * @arg: data passed to the handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * This is the interrupt handler for the i2c driver. Currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * it handles the major interrupts like Rx & Tx FIFO management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * interrupts, master transaction interrupts, arbitration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * bus error interrupts. The rest of the interrupts are treated as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * unhandled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static irqreturn_t i2c_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct nmk_i2c_dev *dev = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 tft, rft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 misr, src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* load Tx FIFO and Rx FIFO threshold values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) tft = readl(dev->virtbase + I2C_TFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rft = readl(dev->virtbase + I2C_RFTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* read interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) misr = readl(dev->virtbase + I2C_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) src = __ffs(misr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch ((1 << src)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Transmit FIFO nearly empty interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case I2C_IT_TXFNE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (dev->cli.operation == I2C_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * in read operation why do we care for writing?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * so disable the Transmit FIFO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) disable_interrupts(dev, I2C_IT_TXFNE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * if done, close the transfer by disabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * corresponding TXFNE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (dev->cli.count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) disable_interrupts(dev, I2C_IT_TXFNE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Rx FIFO nearly full interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * This is set when the numer of entries in Rx FIFO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * greater or equal than the threshold value programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * in RFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case I2C_IT_RXFNF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) for (count = rft; count > 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Read the Rx FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev->cli.buffer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev->cli.count -= rft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev->cli.xfer_bytes += rft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Rx FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case I2C_IT_RXFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev->cli.buffer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Master Transaction Done with/without stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case I2C_IT_MTD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case I2C_IT_MTDWS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (dev->cli.operation == I2C_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) while (!(readl(dev->virtbase + I2C_RISR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) & I2C_IT_RXFE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (dev->cli.count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) *dev->cli.buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) readb(dev->virtbase + I2C_RFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev->cli.buffer++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev->cli.count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev->cli.xfer_bytes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) disable_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clear_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (dev->cli.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(&dev->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "%lu bytes still remain to be xfered\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev->cli.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) (void) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) complete(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Master Arbitration lost interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case I2C_IT_MAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (void) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) complete(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * Bus Error interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * This happens when an unexpected start/stop condition occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * during the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case I2C_IT_BERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* get the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) (void) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) complete(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Tx FIFO overrun interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * This is set when a write operation in Tx FIFO is performed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * the Tx FIFO is full.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) case I2C_IT_TXFOVR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (void) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) complete(&dev->xfer_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* unhandled interrupts by this driver - TODO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) case I2C_IT_TXFE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case I2C_IT_TXFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case I2C_IT_RXFE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case I2C_IT_RFSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case I2C_IT_RFSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) case I2C_IT_WTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) case I2C_IT_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_err(&dev->adev->dev, "unhandled Interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_err(&dev->adev->dev, "spurious Interrupt..\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int nmk_i2c_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int nmk_i2c_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int nmk_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct amba_device *adev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) clk_disable_unprepare(nmk_i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int nmk_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct amba_device *adev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = clk_prepare_enable(nmk_i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(dev, "can't prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ret = init_hw(nmk_i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) clk_disable_unprepare(nmk_i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct dev_pm_ops nmk_i2c_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SET_LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SET_RUNTIME_PM_OPS(nmk_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) nmk_i2c_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const struct i2c_algorithm nmk_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .master_xfer = nmk_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .functionality = nmk_i2c_functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static void nmk_i2c_of_probe(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct nmk_i2c_dev *nmk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* Default to 100 kHz if no frequency is given in the node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* This driver only supports 'standard' and 'fast' modes of operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) nmk->sm = I2C_FREQ_MODE_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) nmk->sm = I2C_FREQ_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) nmk->tft = 1; /* Tx FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) nmk->rft = 8; /* Rx FIFO threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) nmk->timeout = 200; /* Slave response timeout(ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct device_node *np = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct nmk_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct i2c_vendor_data *vendor = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev = devm_kzalloc(&adev->dev, sizeof(struct nmk_i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_err(&adev->dev, "cannot allocate memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev->vendor = vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev->adev = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) nmk_i2c_of_probe(np, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (dev->tft > max_fifo_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev->tft, max_fifo_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev->tft = max_fifo_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (dev->rft > max_fifo_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev->rft, max_fifo_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dev->rft = max_fifo_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) amba_set_drvdata(adev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) resource_size(&adev->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!dev->virtbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev->irq = adev->irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) DRIVER_NAME, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev->clk = devm_clk_get(&adev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_err(&adev->dev, "could not get i2c clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret = clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev_err(&adev->dev, "can't prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) goto err_no_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) adap = &dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) adap->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) adap->dev.parent = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) adap->algo = &nmk_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) adap->timeout = msecs_to_jiffies(dev->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) snprintf(adap->name, sizeof(adap->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "Nomadik I2C at %pR", &adev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_info(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) "initialize %s on virtual base %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) adap->name, dev->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto err_no_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pm_runtime_put(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) err_no_adap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) err_no_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static void nmk_i2c_remove(struct amba_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct resource *res = &adev->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) i2c_del_adapter(&dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) flush_i2c_fifo(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) disable_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clear_all_interrupts(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* disable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) clk_disable_unprepare(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) release_mem_region(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static struct i2c_vendor_data vendor_stn8815 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .has_mtdws = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static struct i2c_vendor_data vendor_db8500 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .has_mtdws = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct amba_id nmk_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .id = 0x00180024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .data = &vendor_stn8815,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .id = 0x00380024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .data = &vendor_db8500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static struct amba_driver nmk_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .pm = &nmk_i2c_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .id_table = nmk_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .probe = nmk_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .remove = nmk_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int __init nmk_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return amba_driver_register(&nmk_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static void __exit nmk_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) amba_driver_unregister(&nmk_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) subsys_initcall(nmk_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) module_exit(nmk_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MODULE_AUTHOR("Sachin Verma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MODULE_AUTHOR("Srinidhi KASAGAR");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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