^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) SMBus driver for nVidia nForce2 MCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Added nForce3 Pro 150 Thomas Leibold <thomas@plx.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) SMBus 2.0 driver for AMD-8111 IO-Hub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Copyright (c) 2002 Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) SUPPORTED DEVICES PCI ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) nForce2 MCP 0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) nForce2 Ultra 400 MCP 0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) nForce3 Pro150 MCP 00D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) nForce3 250Gb MCP 00E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) nForce4 MCP 0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) nForce4 MCP-04 0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) nForce MCP51 0264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) nForce MCP55 0368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) nForce MCP61 03EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) nForce MCP65 0446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) nForce MCP67 0542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) nForce MCP73 07D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) nForce MCP78S 0752
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) nForce MCP79 0AA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) This driver supports the 2 SMBuses that are included in the MCP of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) nForce2/3/4/5xx chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct nforce2_smbus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int blockops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int can_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * nVidia nForce2 SMBus control register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * (Newer incarnations use standard BARs 4 and 5 instead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NFORCE_PCI_SMB1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NFORCE_PCI_SMB2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) check the status of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) the abort command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) abort succeeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NVIDIA_SMB_CTRL_ABORT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NVIDIA_SMB_STS_DONE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define NVIDIA_SMB_STS_ALRM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define NVIDIA_SMB_STS_RES 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NVIDIA_SMB_STS_STATUS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define NVIDIA_SMB_PRTCL_WRITE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define NVIDIA_SMB_PRTCL_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define NVIDIA_SMB_PRTCL_QUICK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NVIDIA_SMB_PRTCL_BYTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NVIDIA_SMB_PRTCL_WORD_DATA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define NVIDIA_SMB_PRTCL_PEC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Misc definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAX_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* We disable the second SMBus channel on these boards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .ident = "DFI Lanparty NF4 Expert",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct pci_driver nforce2_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* For multiplexing support, we need a global reference to the 1st
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SMBus channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if IS_ENABLED(CONFIG_I2C_NFORCE2_S4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_adapter *nforce2_smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL_GPL(nforce2_smbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void nforce2_set_reference(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) nforce2_smbus = adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void nforce2_abort(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct nforce2_smbus *smbus = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_dbg(&adap->dev, "Aborting current transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(&adap->dev, "Can't reset the smbus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int nforce2_check_status(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct nforce2_smbus *smbus = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) temp = inb_p(NVIDIA_SMB_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } while ((!temp) && (timeout++ < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (timeout > MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_dbg(&adap->dev, "SMBus Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (smbus->can_abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) nforce2_abort(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Return negative errno on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 command, int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct nforce2_smbus *smbus = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned char protocol, pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int i, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NVIDIA_SMB_PRTCL_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) protocol |= NVIDIA_SMB_PRTCL_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) read_write = I2C_SMBUS_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outb_p(command, NVIDIA_SMB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) protocol |= NVIDIA_SMB_PRTCL_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) outb_p(command, NVIDIA_SMB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) outb_p(data->byte, NVIDIA_SMB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) outb_p(command, NVIDIA_SMB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outb_p(data->word, NVIDIA_SMB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) outb_p(command, NVIDIA_SMB_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "Transaction failed (requested block size: %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) outb_p(len, NVIDIA_SMB_BCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) outb_p(data->block[i + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) NVIDIA_SMB_DATA + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(&adap->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) outb_p(protocol, NVIDIA_SMB_PRTCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) status = nforce2_check_status(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) data->byte = inb_p(NVIDIA_SMB_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) data->word = inb_p(NVIDIA_SMB_DATA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (inb_p(NVIDIA_SMB_DATA + 1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) len = inb_p(NVIDIA_SMB_BCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "Transaction failed (received block size: 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static u32 nforce2_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* other functionality might be possible, but is not tested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) I2C_FUNC_SMBUS_PEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (((struct nforce2_smbus *)adapter->algo_data)->blockops ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) I2C_FUNC_SMBUS_BLOCK_DATA : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .smbus_xfer = nforce2_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .functionality = nforce2_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct pci_device_id nforce2_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_DEVICE_TABLE(pci, nforce2_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct nforce2_smbus *smbus, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) smbus->base = pci_resource_start(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (smbus->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) smbus->size = pci_resource_len(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Older incarnations of the device used non-standard BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u16 iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (pci_read_config_word(dev, alt_reg, &iobase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) != PCIBIOS_SUCCESSFUL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(&dev->dev, "Error reading PCI config for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) smbus->size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) error = acpi_check_region(smbus->base, smbus->size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) nforce2_driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) smbus->base, smbus->base+smbus->size-1, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) smbus->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) smbus->adapter.algo = &smbus_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) smbus->adapter.algo_data = smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) smbus->adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "SMBus nForce2 adapter at %04x", smbus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) error = i2c_add_adapter(&smbus->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) release_region(smbus->base, smbus->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) smbus->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct nforce2_smbus *smbuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int res1, res2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* we support 2 SMBus adapters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) smbuses = kcalloc(2, sizeof(struct nforce2_smbus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!smbuses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pci_set_drvdata(dev, smbuses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) smbuses[0].blockops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) smbuses[1].blockops = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) smbuses[0].can_abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) smbuses[1].can_abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* SMBus adapter 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (res1 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) smbuses[0].base = 0; /* to have a check value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* SMBus adapter 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (dmi_check_system(nforce2_dmi_blacklist2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) res2 = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) smbuses[1].base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "SMB2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (res2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) smbuses[1].base = 0; /* to have a check value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if ((res1 < 0) && (res2 < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* we did not find even one of the SMBuses, so we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) kfree(smbuses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) nforce2_set_reference(&smbuses[0].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void nforce2_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct nforce2_smbus *smbuses = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) nforce2_set_reference(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (smbuses[0].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i2c_del_adapter(&smbuses[0].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) release_region(smbuses[0].base, smbuses[0].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (smbuses[1].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) i2c_del_adapter(&smbuses[1].adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) release_region(smbuses[1].base, smbuses[1].size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) kfree(smbuses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct pci_driver nforce2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = "nForce2_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .id_table = nforce2_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .probe = nforce2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .remove = nforce2_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) module_pci_driver(nforce2_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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