^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale MXS I2C bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on a (non-working) driver which was:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/stmp_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma/mxs-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_NAME "mxs-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MXS_I2C_CTRL0 (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MXS_I2C_CTRL0_SET (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MXS_I2C_CTRL0_CLR (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MXS_I2C_CTRL0_SFTRST 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MXS_I2C_CTRL0_RUN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MXS_I2C_CTRL0_PIO_MODE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXS_I2C_CTRL0_DIRECTION 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MXS_I2C_TIMING0 (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MXS_I2C_TIMING1 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MXS_I2C_TIMING2 (0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MXS_I2C_CTRL1 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MXS_I2C_CTRL1_SET (0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MXS_I2C_CTRL1_CLR (0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MXS_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MXS_I2C_STAT (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXS_I2C_STAT_GOT_A_NAK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MXS_I2C_STAT_BUS_BUSY 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MXS_I2C_STAT_CLK_GEN_BUSY 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MXS_I2C_DEBUG0_DMAREQ 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MXS_I2C_CTRL1_SLAVE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MXS_I2C_CTRL0_PRE_SEND_START | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MXS_I2C_CTRL0_MASTER_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MXS_I2C_CTRL0_DIRECTION | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MXS_I2C_CTRL0_XFER_COUNT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MXS_I2C_CTRL0_MASTER_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MXS_I2C_CTRL0_DIRECTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MXS_I2C_CTRL0_MASTER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum mxs_i2c_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MXS_I2C_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MXS_I2C_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MXS_I2C_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * struct mxs_i2c_dev - per device, private MXS-I2C data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @dev: driver model device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @dev_type: distinguish i.MX23/i.MX28 features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @regs: IO registers pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @cmd_complete: completion object for transaction wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @cmd_err: error code for last transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @adapter: i2c subsystem adapter node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mxs_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum mxs_i2c_devtype dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint32_t timing0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint32_t timing1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint32_t timing2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* DMA support components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct dma_chan *dmach;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint32_t pio_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t addr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct scatterlist sg_io[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bool dma_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int ret = stmp_reset_block(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Configure timing for the I2C block. The I2C TIMING2 register has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * be programmed with this particular magic number. The rest is derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * from the XTAL speed and requested I2C speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (i2c->dma_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void mxs_i2c_dma_irq_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mxs_i2c_dev *i2c = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) complete(&i2c->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mxs_i2c_dma_finish(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct i2c_msg *msg, uint32_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i2c->addr_data = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) i2c->dma_read = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * SELECT command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Queue the PIO register write transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) desc = dmaengine_prep_slave_sg(i2c->dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (struct scatterlist *)&i2c->pio_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1, DMA_TRANS_NONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "Failed to get PIO reg. write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto select_init_pio_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Queue the DMA data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MXS_DMA_CTRL_WAIT4END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "Failed to get DMA data write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) goto select_init_dma_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * READ command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Queue the PIO register write transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MXS_I2C_CTRL0_XFER_COUNT(msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) desc = dmaengine_prep_slave_sg(i2c->dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (struct scatterlist *)&i2c->pio_data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "Failed to get PIO reg. write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto select_init_dma_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Queue the DMA data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MXS_DMA_CTRL_WAIT4END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "Failed to get DMA data write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto read_init_dma_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) i2c->dma_read = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * WRITE command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Queue the PIO register write transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) desc = dmaengine_prep_slave_sg(i2c->dmach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (struct scatterlist *)&i2c->pio_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 1, DMA_TRANS_NONE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "Failed to get PIO reg. write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto write_init_pio_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Queue the DMA data transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) sg_init_table(i2c->sg_io, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MXS_DMA_CTRL_WAIT4END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "Failed to get DMA data write descriptor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) goto write_init_dma_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * The last descriptor must have this callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * to finish the DMA transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) desc->callback = mxs_i2c_dma_irq_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) desc->callback_param = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Start the transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dma_async_issue_pending(i2c->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Read failpath. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) read_init_dma_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) select_init_dma_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) select_init_pio_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dmaengine_terminate_all(i2c->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Write failpath. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) write_init_dma_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) write_init_pio_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dmaengine_terminate_all(i2c->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (readl(i2c->regs + MXS_I2C_CTRL1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i2c->cmd_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MXS_I2C_CTRL1_SLAVE_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i2c->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return i2c->cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(cmd, i2c->regs + MXS_I2C_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* readback makes sure the write is latched into hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg = readl(i2c->regs + MXS_I2C_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg |= MXS_I2C_CTRL0_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(reg, i2c->regs + MXS_I2C_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * CTRL0::PIO_MODE bit description clarifies the order in which the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * must be written during PIO mode operation. First, the CTRL0 register has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * to be programmed with all the necessary bits but the RUN bit. Then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * payload has to be written into the DATA register. Finally, the transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * is executed by setting the RUN bit in CTRL0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel(cmd, i2c->regs + MXS_I2C_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (i2c->dev_type == MXS_I2C_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(data, i2c->regs + MXS_I2C_DATA(i2c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct i2c_msg *msg, uint32_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) uint32_t data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int i, ret, xlen = 0, xmit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) uint32_t start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Mute IRQs coming from this block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * MX23 idea:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * - Enable CTRL0::PIO_MODE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * - Enable CTRL1::ACK_MODE (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * WARNING! The MX23 is broken in some way, even if it claims
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * to support PIO, when we try to transfer any amount of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * that is not aligned to 4 bytes, the DMA engine will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * transfer. This in turn will mess up the next transfer as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * the block it emit one byte write onto the bus terminated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * with a NAK+STOP. A possible workaround is to reset the IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * block after every PIO transmission, which might just work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * NOTE: The CTRL0::PIO_MODE description is important, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * it outlines how the PIO mode is really supposed to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * PIO READ transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * This transfer MUST be limited to 4 bytes maximum. It is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * possible to transfer more than four bytes via PIO, since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * can not in any way make sure we can read the data from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * DATA register fast enough. Besides, the RX FIFO is only four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * bytes deep, thus we can only really read up to four bytes at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * time. Finally, there is no bit indicating us that new data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * arrived at the FIFO and can thus be fetched from the DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) BUG_ON(msg->len > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* SELECT command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) addr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = mxs_i2c_pio_wait_xfer_end(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "PIO: Failed to send SELECT command!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* READ command. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mxs_i2c_pio_trigger_cmd(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MXS_CMD_I2C_READ | flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MXS_I2C_CTRL0_XFER_COUNT(msg->len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = mxs_i2c_pio_wait_xfer_end(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "PIO: Failed to send READ command!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) data = readl(i2c->regs + MXS_I2C_DATA(i2c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msg->buf[i] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * PIO WRITE transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * The code below implements clock stretching to circumvent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * the possibility of kernel not being able to supply data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * fast enough. It is possible to transfer arbitrary amount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * of data using PIO write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * The LSB of data buffer is the first byte blasted across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * the bus. Higher order bytes follow. Thus the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * filling schematic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) data = addr_data << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Start the transfer with START condition. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) start = MXS_I2C_CTRL0_PRE_SEND_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* If the transfer is long, use clock stretching. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (msg->len > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) data |= (msg->buf[i] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) xmit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* This is the last transfer of the message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (i + 1 == msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Add optional STOP flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) start |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Remove RETAIN_CLOCK bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) xmit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Four bytes are ready in the "data" variable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if ((i & 3) == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) xmit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Nothing interesting happened, continue stuffing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!xmit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Compute the size of the transfer and shift the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * data accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * i = (4k + 0) .... xlen = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * i = (4k + 1) .... xlen = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * i = (4k + 2) .... xlen = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * i = (4k + 3) .... xlen = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((i % 4) == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) xlen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) xlen = (i % 4) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) data >>= (4 - xlen) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) xlen, i, msg->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) writel(MXS_I2C_DEBUG0_DMAREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mxs_i2c_pio_trigger_write_cmd(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) start | MXS_I2C_CTRL0_MASTER_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MXS_I2C_CTRL0_DIRECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* The START condition is sent only once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Wait for the end of the transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = mxs_i2c_pio_wait_xfer_end(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "PIO: Failed to finish WRITE cmd!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Check NAK here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = readl(i2c->regs + MXS_I2C_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MXS_I2C_STAT_GOT_A_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* make sure we capture any occurred error into cmd_err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = mxs_i2c_pio_check_error_state(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Clear any dangling IRQs and re-enable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Clear the PIO_MODE on i.MX23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (i2c->dev_type == MXS_I2C_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Low level master read/write transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int use_pio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msg->addr, msg->len, msg->flags, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * The MX28 I2C IP block can only do PIO READ for transfer of to up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * 4 bytes of length. The write transfer is not limited as it can use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * clock stretching to avoid FIFO underruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) use_pio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) use_pio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) i2c->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (use_pio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* No need to reset the block if NAK was received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret && (ret != -ENXIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mxs_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) reinit_completion(&i2c->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) time_left = wait_for_completion_timeout(&i2c->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msecs_to_jiffies(1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) goto timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = i2c->cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret == -ENXIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * If the transfer fails with a NAK from the slave the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * controller halts until it gets told to return to idle state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) i2c->regs + MXS_I2C_CTRL1_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * WARNING!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * The i.MX23 is strange. After each and every operation, it's I2C IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * block must be reset, otherwise the IP block will misbehave. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * be observed on the bus by the block sending out one single byte onto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * the bus. In case such an error happens, bit 27 will be set in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * and is marked as "TBD" instead. To reset this bit to a correct state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * reset the whole block. Since the block reset does not take long, do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * reset the block after every transfer to play safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (i2c->dev_type == MXS_I2C_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mxs_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_dbg(i2c->dev, "Done with err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(i2c->dev, "Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mxs_i2c_dma_finish(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = mxs_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static u32 mxs_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct mxs_i2c_dev *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) i2c->cmd_err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) i2c->cmd_err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct i2c_algorithm mxs_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .master_xfer = mxs_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .functionality = mxs_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const struct i2c_adapter_quirks mxs_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* The I2C block clock runs at 24MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const uint32_t clk = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) uint32_t divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) uint16_t high_count, low_count, rcv_count, xmit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) uint32_t bus_free, leadin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct device *dev = i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) divider = DIV_ROUND_UP(clk, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (divider < 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * limit the divider, so that min(low_count, high_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * is >= 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) divider = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) speed / 1000, speed % 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) clk / divider / 1000, clk / divider % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) } else if (divider > 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * limit the divider, so that max(low_count, high_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * cannot exceed 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) divider = 1897;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) speed / 1000, speed % 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) clk / divider / 1000, clk / divider % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * The I2C spec specifies the following timing data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * standard mode fast mode Bitfield name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * tLOW (SCL LOW period) 4700 ns 1300 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * tHIGH (SCL HIGH period) 4000 ns 600 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * tSU;DAT (data setup time) 250 ns 100 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * tHD;STA (START hold time) 4000 ns 600 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * tBUF (bus free time) 4700 ns 1300 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * The hardware (of the i.MX28 at least) seems to add 2 additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * clock cycles to the low_count and 7 cycles to the high_count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * This is compensated for by subtracting the respective constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * from the values written to the timing registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (speed > I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rcv_count = high_count * 3 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) xmit_count = low_count * 3 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) speed, clk / divider, divider, low_count, high_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) xmit_count, rcv_count, leadin, bus_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) low_count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) high_count -= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) i2c->timing0 = (high_count << 16) | rcv_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) i2c->timing1 = (low_count << 16) | xmit_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) i2c->timing2 = (bus_free << 16 | leadin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) uint32_t speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct device *dev = i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = of_property_read_u32(node, "clock-frequency", &speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_warn(dev, "No I2C speed selected, using 100kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) speed = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mxs_i2c_derive_timing(i2c, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct platform_device_id mxs_i2c_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .name = "imx23-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .driver_data = MXS_I2C_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .name = "imx28-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .driver_data = MXS_I2C_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }, { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const struct of_device_id mxs_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int mxs_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) of_match_device(mxs_i2c_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct mxs_i2c_dev *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int err, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) const struct platform_device_id *device_id = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) i2c->dev_type = device_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) i2c->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (IS_ERR(i2c->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return PTR_ERR(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2c->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) init_completion(&i2c->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) err = mxs_i2c_get_ofdata(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Setup the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) i2c->dmach = dma_request_chan(dev, "rx-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (IS_ERR(i2c->dmach)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(dev, "Failed to request dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return PTR_ERR(i2c->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Do reset to enforce correct startup after pinmuxing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) err = mxs_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) adap = &i2c->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) adap->algo = &mxs_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) adap->quirks = &mxs_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) adap->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) i2c_set_adapdata(adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) err = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) writel(MXS_I2C_CTRL0_SFTRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) i2c->regs + MXS_I2C_CTRL0_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int mxs_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) i2c_del_adapter(&i2c->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (i2c->dmach)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dma_release_channel(i2c->dmach);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static struct platform_driver mxs_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .of_match_table = mxs_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .probe = mxs_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .remove = mxs_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int __init mxs_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return platform_driver_register(&mxs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) subsys_initcall(mxs_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static void __exit mxs_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) platform_driver_unregister(&mxs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) module_exit(mxs_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_DESCRIPTION("MXS I2C Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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