^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the i2c controller on the Marvell line of host bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Mark A. Greer <mgreer@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2005 (c) MontaVista, Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mv643xx_i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Ctlr status values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MV64XXX_I2C_STATUS_MAST_START 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Register defines (I2C bridge) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Bridge Control values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Bridge Status values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Driver states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MV64XXX_I2C_STATE_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MV64XXX_I2C_STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Driver actions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MV64XXX_I2C_ACTION_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MV64XXX_I2C_ACTION_CONTINUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MV64XXX_I2C_ACTION_SEND_RESTART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MV64XXX_I2C_ACTION_SEND_ADDR_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MV64XXX_I2C_ACTION_SEND_ADDR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MV64XXX_I2C_ACTION_SEND_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MV64XXX_I2C_ACTION_RCV_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MV64XXX_I2C_ACTION_RCV_DATA_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MV64XXX_I2C_ACTION_SEND_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mv64xxx_i2c_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 ext_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mv64xxx_i2c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_msg *msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 aborting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 cntl_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mv64xxx_i2c_regs reg_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 addr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 byte_posn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 send_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 freq_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 freq_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk *reg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bool offload_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* 5us delay in order to avoid repeated start timing violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool errata_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool irq_clear_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Clk div is 2 to the power n, not 2 to the power n + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool clk_n_base_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .addr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .ext_addr = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .data = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .control = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .status = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .clock = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .soft_reset = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .addr = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .ext_addr = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .data = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .control = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .status = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .clock = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .soft_reset = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) drv_data->addr2 = (u32)msg->addr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) drv_data->addr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Finite State Machine & Interrupt Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Reset hardware and initialize FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (drv_data->offload_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(0, drv_data->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(0, drv_data->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) drv_data->reg_base + drv_data->reg_offsets.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * If state is idle, then this is likely the remnants of an old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * operation that driver has given up on or the user has killed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * If so, issue the stop condition and go to idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* The status from the ctlr [mostly] tells us what to do next */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Start condition interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Performing a write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (drv_data->msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) drv_data->state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if ((drv_data->bytes_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) || (drv_data->aborting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) && (drv_data->byte_posn != 0))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (drv_data->send_stop || drv_data->aborting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) drv_data->action =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MV64XXX_I2C_ACTION_SEND_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) drv_data->state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) drv_data->state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) drv_data->bytes_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Performing a read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (drv_data->msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) drv_data->state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (drv_data->bytes_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) drv_data->bytes_left--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if ((drv_data->bytes_left == 1) || drv_data->aborting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Doesn't seem to be a device at other end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) drv_data->rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(&drv_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) drv_data->state, status, drv_data->msg->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) drv_data->msg->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mv64xxx_i2c_hw_init(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) drv_data->rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) drv_data->msg = drv_data->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) drv_data->byte_posn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) drv_data->bytes_left = drv_data->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) drv_data->aborting = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) drv_data->rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) switch(drv_data->action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case MV64XXX_I2C_ACTION_SEND_RESTART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* We should only get here if we have further messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BUG_ON(drv_data->num_msgs == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) drv_data->msgs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) drv_data->num_msgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mv64xxx_i2c_send_start(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (drv_data->errata_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * We're never at the start of the message here, and by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * time it's already too late to do any protocol mangling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Thankfully, do not advertise support for that feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) drv_data->send_stop = drv_data->num_msgs == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case MV64XXX_I2C_ACTION_CONTINUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writel(drv_data->cntl_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case MV64XXX_I2C_ACTION_SEND_ADDR_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(drv_data->addr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) drv_data->reg_base + drv_data->reg_offsets.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel(drv_data->cntl_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case MV64XXX_I2C_ACTION_SEND_ADDR_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(drv_data->addr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) drv_data->reg_base + drv_data->reg_offsets.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(drv_data->cntl_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case MV64XXX_I2C_ACTION_SEND_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(drv_data->msg->buf[drv_data->byte_posn++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) drv_data->reg_base + drv_data->reg_offsets.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(drv_data->cntl_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case MV64XXX_I2C_ACTION_RCV_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) drv_data->msg->buf[drv_data->byte_posn++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) readl(drv_data->reg_base + drv_data->reg_offsets.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(drv_data->cntl_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) drv_data->msg->buf[drv_data->byte_posn++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) readl(drv_data->reg_base + drv_data->reg_offsets.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) drv_data->block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (drv_data->errata_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) wake_up(&drv_data->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case MV64XXX_I2C_ACTION_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(&drv_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "mv64xxx_i2c_do_action: Invalid action: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) drv_data->action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) drv_data->rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case MV64XXX_I2C_ACTION_SEND_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) drv_data->block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) wake_up(&drv_data->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) memcpy(msg->buf, buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 cause, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) cause = readl(drv_data->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!cause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) status = readl(drv_data->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MV64XXX_I2C_REG_BRIDGE_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) drv_data->rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) drv_data->rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Transaction is a one message read transaction, read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * for this message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) drv_data->msgs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) drv_data->num_msgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Transaction is a two messages write/read transaction, read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * data for the second (read) message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else if (drv_data->num_msgs == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) !(drv_data->msgs[0].flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) drv_data->msgs[1].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) drv_data->msgs += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) drv_data->num_msgs -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(0, drv_data->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) drv_data->block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) wake_up(&drv_data->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) mv64xxx_i2c_intr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct mv64xxx_i2c_data *drv_data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) irqreturn_t rc = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) spin_lock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (drv_data->offload_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rc = mv64xxx_i2c_intr_offload(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MV64XXX_I2C_REG_CONTROL_IFLG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mv64xxx_i2c_fsm(drv_data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mv64xxx_i2c_do_action(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (drv_data->irq_clear_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) drv_data->reg_base + drv_data->reg_offsets.control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rc = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * I2C Msg Execution Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) char abort = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) time_left = wait_event_timeout(drv_data->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) !drv_data->block, drv_data->adapter.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) spin_lock_irqsave(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!time_left) { /* Timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) drv_data->rc = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) } else if (time_left < 0) { /* Interrupted/Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) drv_data->rc = time_left; /* errno value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (abort && drv_data->block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) drv_data->aborting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) spin_unlock_irqrestore(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) time_left = wait_event_timeout(drv_data->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) !drv_data->block, drv_data->adapter.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if ((time_left <= 0) && drv_data->block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) drv_data->state = MV64XXX_I2C_STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(&drv_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "mv64xxx: I2C bus locked, block: %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "time_left: %d\n", drv_data->block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (int)time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mv64xxx_i2c_hw_init(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) spin_unlock_irqrestore(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int is_last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) spin_lock_irqsave(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) drv_data->send_stop = is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) drv_data->block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mv64xxx_i2c_send_start(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) spin_unlock_irqrestore(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mv64xxx_i2c_wait_for_completion(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return drv_data->rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct i2c_msg *msg = drv_data->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) memcpy(buf, msg->buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct i2c_msg *msgs = drv_data->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int num = drv_data->num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned long ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) spin_lock_irqsave(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Build transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (msgs[0].flags & I2C_M_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Single write message transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) size_t len = msgs[0].len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mv64xxx_i2c_prepare_tx(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Single read message transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else if (num == 1 && msgs[0].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) size_t len = msgs[0].len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * Transaction with one write and one read message. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * guaranteed by the mv64xx_i2c_can_offload() checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else if (num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) size_t lentx = msgs[0].len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) size_t lenrx = msgs[1].len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctrl_reg |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MV64XXX_I2C_BRIDGE_CONTROL_RD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MV64XXX_I2C_BRIDGE_CONTROL_WR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mv64xxx_i2c_prepare_tx(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Execute transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) drv_data->block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_unlock_irqrestore(&drv_data->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mv64xxx_i2c_wait_for_completion(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return drv_data->rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return msg->len <= 8 && msg->len >= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct i2c_msg *msgs = drv_data->msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int num = drv_data->num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!drv_data->offload_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * We can offload a transaction consisting of a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * message, as long as the message has a length between 1 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * 8 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * We can offload a transaction consisting of two messages, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * the first is a write and a second is a read, and both have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * a length between 1 and 8 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (num == 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mv64xxx_i2c_valid_offload_sz(msgs) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) !(msgs[0].flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) msgs[1].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * I2C Core Support Routines (Interface to higher level I2C code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mv64xxx_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int rc, ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) BUG_ON(drv_data->msgs != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) drv_data->msgs = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) drv_data->num_msgs = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (mv64xxx_i2c_can_offload(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) rc = mv64xxx_i2c_offload_xfer(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) drv_data->num_msgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) drv_data->msgs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const struct i2c_algorithm mv64xxx_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .master_xfer = mv64xxx_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .functionality = mv64xxx_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Driver Interface & Early Init Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) const int tclk, const int n, const int m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (drv_data->clk_n_base_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return tclk / (10 * (m + 1) * (1 << n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return tclk / (10 * (m + 1) * (2 << n));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const u32 req_freq, const u32 tclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) int freq, delta, best_delta = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int m, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) for (n = 0; n <= 7; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) for (m = 0; m <= 15; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) delta = req_freq - freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (delta >= 0 && delta < best_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) drv_data->freq_m = m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) drv_data->freq_n = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) best_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (best_delta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (best_delta == INT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) const struct of_device_id *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 bus_freq, tclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* CLK is mandatory when using DT to describe the i2c bus. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * need to know tclk in order to calculate bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * factors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (IS_ERR(drv_data->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) tclk = clk_get_rate(drv_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (of_property_read_u32(np, "clock-frequency", &bus_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) drv_data->clk_n_base_0 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (IS_ERR(drv_data->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rc = PTR_ERR(drv_data->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) reset_control_deassert(drv_data->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Its not yet defined how timeouts will be specified in device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * So hard code the value to 1 second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) drv_data->adapter.timeout = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) device = of_match_device(mv64xxx_i2c_of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * For controllers embedded in new SoCs activate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Transaction Generator support and the errata fix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) drv_data->offload_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* The delay is only needed in standard mode (100kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) drv_data->errata_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) drv_data->offload_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* The delay is only needed in standard mode (100kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) drv_data->errata_delay = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) drv_data->irq_clear_inverted = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #else /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) mv64xxx_i2c_probe(struct platform_device *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct mv64xxx_i2c_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if ((!pdata && !pd->dev.of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!drv_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (IS_ERR(drv_data->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return PTR_ERR(drv_data->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) sizeof(drv_data->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) init_waitqueue_head(&drv_data->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) spin_lock_init(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Not all platforms have clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) drv_data->clk = devm_clk_get(&pd->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!IS_ERR(drv_data->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clk_prepare_enable(drv_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!IS_ERR(drv_data->reg_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) clk_prepare_enable(drv_data->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) drv_data->irq = platform_get_irq(pd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) drv_data->freq_m = pdata->freq_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) drv_data->freq_n = pdata->freq_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) drv_data->offload_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else if (pd->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) rc = mv64xxx_of_config(drv_data, &pd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto exit_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (drv_data->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) rc = drv_data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) goto exit_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) drv_data->adapter.dev.parent = &pd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) drv_data->adapter.algo = &mv64xxx_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) drv_data->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) drv_data->adapter.class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) drv_data->adapter.nr = pd->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) drv_data->adapter.dev.of_node = pd->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) platform_set_drvdata(pd, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) i2c_set_adapdata(&drv_data->adapter, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mv64xxx_i2c_hw_init(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MV64XXX_I2C_CTLR_NAME, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(&drv_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "mv64xxx: Can't register intr handler irq%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) drv_data->irq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto exit_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(&drv_data->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto exit_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) exit_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) free_irq(drv_data->irq, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) exit_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) reset_control_assert(drv_data->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) exit_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) clk_disable_unprepare(drv_data->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) clk_disable_unprepare(drv_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mv64xxx_i2c_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) i2c_del_adapter(&drv_data->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) free_irq(drv_data->irq, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) reset_control_assert(drv_data->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) clk_disable_unprepare(drv_data->reg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) clk_disable_unprepare(drv_data->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int mv64xxx_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mv64xxx_i2c_hw_init(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct dev_pm_ops mv64xxx_i2c_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .resume = mv64xxx_i2c_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define mv64xxx_i2c_pm_ops NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static struct platform_driver mv64xxx_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .probe = mv64xxx_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .remove = mv64xxx_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .name = MV64XXX_I2C_CTLR_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .pm = mv64xxx_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .of_match_table = mv64xxx_i2c_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) module_platform_driver(mv64xxx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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