^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/i2c/busses/i2c-mt7621.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (C) 2014 Sittisak <sittisaks@hotmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_SM0CFG2_REG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_SM0CTL0_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_SM0CTL1_REG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_SM0D0_REG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_SM0D1_REG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_PINTEN_REG 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_PINTST_REG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_PINTCL_REG 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* REG_SM0CFG2_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SM0CFG2_IS_AUTOMODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* REG_SM0CTL0_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SM0CTL0_ODRAIN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SM0CTL0_CLK_DIV_MASK (0x7ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SM0CTL0_CLK_DIV_MAX 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SM0CTL0_CS_STATUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SM0CTL0_SCL_STATE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SM0CTL0_SDA_STATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SM0CTL0_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SM0CTL0_SCL_STRETCH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* REG_SM0CTL1_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SM0CTL1_ACK_MASK (0xff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SM0CTL1_PGLEN_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SM0CTL1_PGLEN(x) ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SM0CTL1_READ (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SM0CTL1_READ_LAST (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SM0CTL1_STOP (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SM0CTL1_WRITE (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SM0CTL1_START (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SM0CTL1_MODE_MASK (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SM0CTL1_TRI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* timeout waiting for I2C devices to respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct mtk_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 bus_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val, !(val & SM0CTL1_TRI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 10, TIMEOUT_MS * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_dbg(i2c->dev, "idle err(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void mtk_i2c_reset(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = device_reset(i2c->adap.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(i2c->dev, "I2C reset failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * configure open-drain mode, this bit needs to be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) iowrite32(0, i2c->base + REG_SM0CFG2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ioread32(i2c->base + REG_SM0CFG2_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ioread32(i2c->base + REG_SM0CTL0_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ioread32(i2c->base + REG_SM0CTL1_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ioread32(i2c->base + REG_SM0D0_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ioread32(i2c->base + REG_SM0D1_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int mtk_i2c_master_start(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return mtk_i2c_wait_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int mtk_i2c_master_stop(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return mtk_i2c_wait_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) i2c->base + REG_SM0CTL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return mtk_i2c_wait_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct mtk_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int i, j, ret, len, page_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* wait hardware idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = mtk_i2c_wait_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* start sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = mtk_i2c_master_start(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* write address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (pmsg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 10 bits address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) addr |= (pmsg->addr & 0xff) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (pmsg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) addr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) iowrite32(addr, i2c->base + REG_SM0D0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* 7 bits address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) addr = i2c_8bit_addr_from_msg(pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) iowrite32(addr, i2c->base + REG_SM0D0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* check address ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = mtk_i2c_check_ack(i2c, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* transfer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) page_len = (len >= 8) ? 8 : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cmd = (len > 8) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SM0CTL1_READ : SM0CTL1_READ_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) memcpy(data, &pmsg->buf[j], page_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) iowrite32(data[0], i2c->base + REG_SM0D0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) iowrite32(data[1], i2c->base + REG_SM0D1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cmd = SM0CTL1_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = mtk_i2c_master_cmd(i2c, cmd, page_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) data[0] = ioread32(i2c->base + REG_SM0D0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data[1] = ioread32(i2c->base + REG_SM0D1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) memcpy(&pmsg->buf[j], data, page_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = mtk_i2c_check_ack(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (1 << page_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto err_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = mtk_i2c_master_stop(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* the return value is number of executed messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) err_ack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = mtk_i2c_master_stop(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto err_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err_timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mtk_i2c_dump_reg(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mtk_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static u32 mtk_i2c_func(struct i2c_adapter *a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct i2c_algorithm mtk_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .master_xfer = mtk_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .functionality = mtk_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct of_device_id i2c_mtk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .compatible = "mediatek,mt7621-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void mtk_i2c_init(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (i2c->clk_div < 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) i2c->clk_div = 99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mtk_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mtk_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct mtk_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) i2c->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (IS_ERR(i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return PTR_ERR(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(&pdev->dev, "no clock defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return PTR_ERR(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(&pdev->dev, "Unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) &i2c->bus_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) i2c->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (i2c->bus_freq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_warn(i2c->dev, "clock-frequency 0 not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) adap = &i2c->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) adap->algo = &mtk_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) i2c_set_adapdata(adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mtk_i2c_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int mtk_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct mtk_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct platform_driver mtk_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .probe = mtk_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .remove = mtk_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "i2c-mt7621",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .of_match_table = i2c_mtk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) module_platform_driver(mtk_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_AUTHOR("Steven Liu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_DESCRIPTION("MT7621 I2C host driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_ALIAS("platform:MT7621-I2C");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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