^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Xudong Chen <xudong.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_RS_TRANSFER (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_ARB_LOST (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_HS_NACKERR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_ACKERR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_TRANSAC_COMP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_TRANSAC_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_RS_MUL_CNFG (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_RS_MUL_TRIG (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_DCM_DISABLE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_IO_CONFIG_PUSH_PULL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_SOFT_RST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_HANDSHAKE_RST 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_FIFO_ADDR_CLR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_DELAY_LEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_ST_START_CON 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_FS_START_CON 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_TIME_CLR_VALUE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_TIME_DEFAULT_VALUE 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_WRRD_TRANAC_VALUE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_RD_TRANAC_VALUE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_SCL_MIS_COMP_VALUE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_CHN_CLR_FLAG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_DMA_CON_TX 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_DMA_CON_RX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_DMA_ASYNC_MODE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_DMA_SKIP_CONFIG 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_DMA_DIR_CHANGE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_DMA_START_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_DMA_INT_FLAG_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_DMA_CLR_FLAG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_DMA_WARM_RST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_DMA_HARD_RST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_DMA_HANDSHAKE_RST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX_SAMPLE_CNT_DIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX_STEP_CNT_DIV 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX_CLOCK_DIV 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX_HS_STEP_CNT_DIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_STANDARD_MODE_BUFFER (1000 / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_FAST_MODE_BUFFER (300 / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2C_FAST_MODE_PLUS_BUFFER (20 / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2C_CONTROL_RS (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2C_CONTROL_DMA_EN (0x1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2C_CONTROL_DMAACK_EN (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2C_CONTROL_ASYNC_MODE (0x1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2C_CONTROL_WRAPPER (0x1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C_DRV_NAME "i2c-mt65xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum DMA_REGS_OFFSET {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) OFFSET_INT_FLAG = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) OFFSET_INT_EN = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) OFFSET_EN = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) OFFSET_RST = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) OFFSET_CON = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) OFFSET_TX_MEM_ADDR = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) OFFSET_RX_MEM_ADDR = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) OFFSET_TX_LEN = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) OFFSET_RX_LEN = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) OFFSET_TX_4G_MODE = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) OFFSET_RX_4G_MODE = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum i2c_trans_st_rs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) I2C_TRANS_STOP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) I2C_TRANS_REPEATED_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum mtk_trans_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) I2C_MASTER_WR = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) I2C_MASTER_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) I2C_MASTER_WRRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum I2C_REGS_OFFSET {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) OFFSET_DATA_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) OFFSET_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OFFSET_INTR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OFFSET_INTR_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) OFFSET_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) OFFSET_TRANSFER_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) OFFSET_TRANSAC_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) OFFSET_DELAY_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) OFFSET_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) OFFSET_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OFFSET_EXT_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) OFFSET_FIFO_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OFFSET_FIFO_THRESH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OFFSET_FIFO_ADDR_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) OFFSET_IO_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) OFFSET_RSV_DEBUG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) OFFSET_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) OFFSET_SOFTRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) OFFSET_DCM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) OFFSET_PATH_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) OFFSET_DEBUGSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) OFFSET_DEBUGCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OFFSET_TRANSFER_LEN_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OFFSET_CLOCK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OFFSET_LTIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OFFSET_SCL_HIGH_LOW_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) OFFSET_HS_SCL_HIGH_LOW_RATIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) OFFSET_SCL_MIS_COMP_POINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) OFFSET_STA_STO_AC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) OFFSET_HS_STA_STO_AC_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) OFFSET_SDA_TIMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const u16 mt_i2c_regs_v1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [OFFSET_DATA_PORT] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [OFFSET_SLAVE_ADDR] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [OFFSET_INTR_MASK] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [OFFSET_INTR_STAT] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [OFFSET_CONTROL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [OFFSET_TRANSFER_LEN] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [OFFSET_TRANSAC_LEN] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [OFFSET_DELAY_LEN] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [OFFSET_TIMING] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [OFFSET_START] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [OFFSET_EXT_CONF] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [OFFSET_FIFO_STAT] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [OFFSET_FIFO_THRESH] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [OFFSET_FIFO_ADDR_CLR] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [OFFSET_IO_CONFIG] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [OFFSET_RSV_DEBUG] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [OFFSET_HS] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [OFFSET_SOFTRESET] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [OFFSET_DCM_EN] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [OFFSET_PATH_DIR] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [OFFSET_DEBUGSTAT] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [OFFSET_DEBUGCTRL] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [OFFSET_CLOCK_DIV] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [OFFSET_STA_STO_AC_TIMING] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [OFFSET_SDA_TIMING] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const u16 mt_i2c_regs_v2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [OFFSET_DATA_PORT] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [OFFSET_SLAVE_ADDR] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [OFFSET_INTR_MASK] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [OFFSET_INTR_STAT] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [OFFSET_CONTROL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [OFFSET_TRANSFER_LEN] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [OFFSET_TRANSAC_LEN] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [OFFSET_DELAY_LEN] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [OFFSET_TIMING] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [OFFSET_START] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [OFFSET_EXT_CONF] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [OFFSET_LTIMING] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [OFFSET_HS] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [OFFSET_IO_CONFIG] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [OFFSET_FIFO_ADDR_CLR] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [OFFSET_SDA_TIMING] = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [OFFSET_TRANSFER_LEN_AUX] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [OFFSET_CLOCK_DIV] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [OFFSET_SOFTRESET] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [OFFSET_DEBUGSTAT] = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [OFFSET_DEBUGCTRL] = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [OFFSET_FIFO_STAT] = 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [OFFSET_FIFO_THRESH] = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [OFFSET_DCM_EN] = 0xf88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mtk_i2c_compatible {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) const struct i2c_adapter_quirks *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const u16 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned char pmic_i2c: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned char dcm: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char auto_restart: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned char aux_len_reg: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned char timing_adjust: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned char dma_sync: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned char ltiming_adjust: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned char apdma_sync: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char max_dma_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mtk_i2c_ac_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 htiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 ltiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 inter_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 scl_hl_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u16 hs_scl_hl_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 sta_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 hs_sta_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u16 sda_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct mtk_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct i2c_adapter adap; /* i2c host adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* set in i2c probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *base; /* i2c base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void __iomem *pdmabase; /* dma base address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct clk *clk_main; /* main clock for i2c bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk *clk_dma; /* DMA clock for i2c via DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *clk_arb; /* Arbitrator clock for i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) bool have_pmic; /* can use i2c pins from PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool use_push_pull; /* IO config push-pull mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 irq_stat; /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int clk_src_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int speed_hz; /* The speed in transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum mtk_trans_op op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u16 timing_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u16 high_speed_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u16 ltiming_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned char auto_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool ignore_restart_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mtk_i2c_ac_timing ac_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct mtk_i2c_compatible *dev_comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * struct i2c_spec_values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @min_low_ns: min LOW period of the SCL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @min_su_sta_ns: min set-up time for a repeated START condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @max_hd_dat_ns: max data hold time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @min_su_dat_ns: min data set-up time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct i2c_spec_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int min_low_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int min_su_sta_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int max_hd_dat_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int min_su_dat_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct i2c_spec_values standard_mode_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct i2c_spec_values fast_mode_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct i2c_spec_values fast_mode_plus_spec = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .max_num_msgs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .max_write_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .max_read_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .max_comb_1st_msg_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .max_comb_2nd_msg_len = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .max_num_msgs = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct mtk_i2c_compatible mt2712_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .regs = mt_i2c_regs_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .dcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .auto_restart = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .aux_len_reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .timing_adjust = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .dma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .ltiming_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .max_dma_support = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct mtk_i2c_compatible mt6577_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .quirks = &mt6577_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .regs = mt_i2c_regs_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .dcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .auto_restart = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .aux_len_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .timing_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .dma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .ltiming_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .max_dma_support = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct mtk_i2c_compatible mt6589_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .quirks = &mt6577_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .regs = mt_i2c_regs_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pmic_i2c = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .dcm = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .auto_restart = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .aux_len_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .timing_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .dma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .ltiming_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .max_dma_support = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct mtk_i2c_compatible mt7622_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .quirks = &mt7622_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .regs = mt_i2c_regs_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .dcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .auto_restart = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .aux_len_reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .timing_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .dma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .ltiming_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .max_dma_support = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct mtk_i2c_compatible mt8173_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .regs = mt_i2c_regs_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .dcm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .auto_restart = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .aux_len_reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .timing_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .dma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .ltiming_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .max_dma_support = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct mtk_i2c_compatible mt8183_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .quirks = &mt8183_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .regs = mt_i2c_regs_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .dcm = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .auto_restart = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .aux_len_reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .timing_adjust = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .dma_sync = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .ltiming_adjust = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .apdma_sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .max_dma_support = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct mtk_i2c_compatible mt8192_compat = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .quirks = &mt8183_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .regs = mt_i2c_regs_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .pmic_i2c = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .dcm = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .auto_restart = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .aux_len_reg = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .timing_adjust = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .dma_sync = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ltiming_adjust = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .apdma_sync = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .max_dma_support = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct of_device_id mtk_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return readw(i2c->base + i2c->dev_comp->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) enum I2C_REGS_OFFSET reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writew(val, i2c->base + i2c->dev_comp->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = clk_prepare_enable(i2c->clk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = clk_prepare_enable(i2c->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) goto err_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (i2c->have_pmic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = clk_prepare_enable(i2c->clk_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err_pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (i2c->clk_arb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = clk_prepare_enable(i2c->clk_arb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto err_arb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) err_arb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (i2c->have_pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) clk_disable_unprepare(i2c->clk_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) err_pmic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clk_disable_unprepare(i2c->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err_main:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_disable_unprepare(i2c->clk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (i2c->clk_arb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clk_disable_unprepare(i2c->clk_arb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (i2c->have_pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clk_disable_unprepare(i2c->clk_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clk_disable_unprepare(i2c->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clk_disable_unprepare(i2c->clk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u16 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u16 intr_stat_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 ext_conf_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (i2c->dev_comp->apdma_sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) OFFSET_SOFTRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Set ioconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (i2c->use_push_pull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (i2c->dev_comp->dcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (i2c->dev_comp->ltiming_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ext_conf_val = I2C_ST_START_CON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ext_conf_val = I2C_FS_START_CON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (i2c->dev_comp->timing_adjust) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ext_conf_val = i2c->ac_timing.ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) OFFSET_CLOCK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) OFFSET_SCL_MIS_COMP_POINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) OFFSET_SDA_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (i2c->dev_comp->ltiming_adjust) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) OFFSET_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) OFFSET_LTIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) OFFSET_SCL_HIGH_LOW_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) OFFSET_HS_SCL_HIGH_LOW_RATIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) OFFSET_STA_STO_AC_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) OFFSET_HS_STA_STO_AC_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (i2c->have_pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) control_reg = I2C_CONTROL_ACKERR_DET_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (i2c->dev_comp->dma_sync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return &standard_mode_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) else if (speed <= I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return &fast_mode_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return &fast_mode_plus_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int mtk_i2c_max_step_cnt(unsigned int target_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return MAX_HS_STEP_CNT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return MAX_STEP_CNT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Check and Calculate i2c ac-timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Hardware design:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * xxx_cnt_div = spec->min_xxx_ns / sample_ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Sample_ns is rounded down for xxx_cnt_div would be greater
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * than the smallest spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * The sda_timing is chosen as the middle value between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * the largest and smallest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int check_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int step_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int sample_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) const struct i2c_spec_values *spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) clk_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!i2c->dev_comp->timing_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (i2c->dev_comp->ltiming_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) max_sta_cnt = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spec = mtk_i2c_get_spec(check_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (i2c->dev_comp->ltiming_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) clk_ns = 1000000000 / clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_ns = sample_ns / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns, clk_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (su_sta_cnt > max_sta_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (low_cnt > step_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) high_cnt = 2 * step_cnt - low_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) high_cnt = step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) low_cnt = step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) sda_max = spec->max_hd_dat_ns / sample_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (sda_max > low_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) sda_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (sda_min < low_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) sda_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (sda_min > sda_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (i2c->dev_comp->ltiming_adjust) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (sample_cnt << 12) | (high_cnt << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) i2c->ac_timing.ltiming |= (sample_cnt << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (low_cnt << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) i2c->ac_timing.ext &= ~GENMASK(7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) (high_cnt << 6) | low_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) su_sta_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) i2c->ac_timing.sda_timing |= (1 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ((sda_max + sda_min) / 2) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (i2c->dev_comp->ltiming_adjust) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) i2c->ac_timing.scl_hl_ratio = (1 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (high_cnt << 6) | low_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) su_sta_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) i2c->ac_timing.sda_timing = (1 << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) (sda_max + sda_min) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Calculate i2c port speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Hardware design:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * clock_div: fixed in hardware, but may be various in different SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * The calculation want to pick the highest bus frequency that is still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * less than or equal to i2c->speed_hz. The calculation try to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * sample_cnt and step_cn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned int target_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int *timing_step_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int *timing_sample_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int max_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned int base_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned int opt_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int best_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int cnt_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) base_step_cnt = max_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Find the best combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Search for the best pair (sample_cnt, step_cnt) with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * 0 < step_cnt < max_step_cnt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * sample_cnt * step_cnt >= opt_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * optimizing for sample_cnt * step_cnt being minimal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) cnt_mul = step_cnt * sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (step_cnt > max_step_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (cnt_mul < best_mul) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = mtk_i2c_check_ac_timing(i2c, clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) target_speed, step_cnt - 1, sample_cnt - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) best_mul = cnt_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) base_sample_cnt = sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) base_step_cnt = step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (best_mul == opt_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) sample_cnt = base_sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) step_cnt = base_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* In this case, hardware can't support such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * low i2c_bus_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *timing_step_cnt = step_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *timing_sample_cnt = sample_cnt - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned int clk_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned int step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned int sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) unsigned int l_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int l_sample_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned int target_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int max_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) target_speed = i2c->speed_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) parent_clk /= i2c->clk_src_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (i2c->dev_comp->timing_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) max_clk_div = MAX_CLOCK_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) max_clk_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) clk_src = parent_clk / clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Set master code speed register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = mtk_i2c_calculate_speed(i2c, clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) I2C_MAX_FAST_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) &l_step_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &l_sample_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Set the high speed mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = mtk_i2c_calculate_speed(i2c, clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) target_speed, &step_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &sample_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) (sample_cnt << 12) | (step_cnt << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (i2c->dev_comp->ltiming_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) i2c->ltiming_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) (l_sample_cnt << 6) | l_step_cnt |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (sample_cnt << 12) | (step_cnt << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = mtk_i2c_calculate_speed(i2c, clk_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) target_speed, &l_step_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) &l_sample_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Disable the high speed transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (i2c->dev_comp->ltiming_adjust)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i2c->ltiming_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) (l_sample_cnt << 6) | l_step_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) i2c->ac_timing.inter_clk_div = clk_div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) int num, int left_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u16 addr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u16 start_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u16 control_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u16 restart_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u16 dma_sync = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 reg_4g_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u8 *dma_rd_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 *dma_wr_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dma_addr_t rpaddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dma_addr_t wpaddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) i2c->irq_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (i2c->auto_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) restart_flag = I2C_RS_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) reinit_completion(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) control_reg |= I2C_CONTROL_RS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (i2c->op == I2C_MASTER_WRRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) addr_reg = i2c_8bit_addr_from_msg(msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Set transfer and transaction len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (i2c->op == I2C_MASTER_WRRD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (i2c->dev_comp->aux_len_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mtk_i2c_writew(i2c, (msgs + 1)->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) OFFSET_TRANSFER_LEN_AUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) OFFSET_TRANSFER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (i2c->dev_comp->apdma_sync) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (i2c->op == I2C_MASTER_WRRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dma_sync |= I2C_DMA_DIR_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Prepare buffer data to start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (i2c->op == I2C_MASTER_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!dma_rd_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) msgs->len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (dma_mapping_error(i2c->dev, rpaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (i2c->dev_comp->max_dma_support > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) reg_4g_mode = upper_32_bits(rpaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) } else if (i2c->op == I2C_MASTER_WR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!dma_wr_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) msgs->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (dma_mapping_error(i2c->dev, wpaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (i2c->dev_comp->max_dma_support > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) reg_4g_mode = upper_32_bits(wpaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (!dma_wr_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) msgs->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (dma_mapping_error(i2c->dev, wpaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!dma_rd_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dma_unmap_single(i2c->dev, wpaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) msgs->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) (msgs + 1)->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (dma_mapping_error(i2c->dev, rpaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dma_unmap_single(i2c->dev, wpaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) msgs->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (i2c->dev_comp->max_dma_support > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) reg_4g_mode = upper_32_bits(wpaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) reg_4g_mode = upper_32_bits(rpaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!i2c->auto_restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) start_reg = I2C_TRANSAC_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (left_num >= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) start_reg |= I2C_RS_MUL_CNFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mtk_i2c_writew(i2c, start_reg, OFFSET_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = wait_for_completion_timeout(&i2c->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) i2c->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Clear interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (i2c->op == I2C_MASTER_WR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dma_unmap_single(i2c->dev, wpaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) msgs->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) } else if (i2c->op == I2C_MASTER_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dma_unmap_single(i2c->dev, rpaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) msgs->len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dma_unmap_single(i2c->dev, wpaddr, msgs->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mtk_i2c_init_hw(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) mtk_i2c_init_hw(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int mtk_i2c_transfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int left_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct mtk_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = mtk_i2c_clock_enable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) i2c->auto_restart = i2c->dev_comp->auto_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* checking if we can skip restart and optimize using WRRD mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (i2c->auto_restart && num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) msgs[0].addr == msgs[1].addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) i2c->auto_restart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (i2c->auto_restart && num >= 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* ignore the first restart irq after the master code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * otherwise the first transfer will be discarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) i2c->ignore_restart_irq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) i2c->ignore_restart_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) while (left_num--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!msgs->buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dev_dbg(i2c->dev, "data buffer is NULL.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (msgs->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) i2c->op = I2C_MASTER_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) i2c->op = I2C_MASTER_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!i2c->auto_restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (num > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* combined two messages into one transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) i2c->op = I2C_MASTER_WRRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) left_num--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* always use DMA mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) msgs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* the return value is number of executed messages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mtk_i2c_clock_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct mtk_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) u16 restart_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u16 intr_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (i2c->auto_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) restart_flag = I2C_RS_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * when occurs ack error, i2c controller generate two interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * first is the ack error interrupt, then the complete interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * i2c->irq_stat need keep the two interrupt value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) i2c->irq_stat |= intr_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) i2c->ignore_restart_irq = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) i2c->irq_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) I2C_TRANSAC_START, OFFSET_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) complete(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static const struct i2c_algorithm mtk_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .master_xfer = mtk_i2c_transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .functionality = mtk_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (i2c->clk_src_div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) i2c->use_push_pull =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) of_property_read_bool(np, "mediatek,use-push-pull");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int mtk_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct mtk_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) i2c->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (IS_ERR(i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return PTR_ERR(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (IS_ERR(i2c->pdmabase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return PTR_ERR(i2c->pdmabase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) init_completion(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) i2c->dev_comp = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) i2c->adap.algo = &mtk_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) i2c->adap.quirks = i2c->dev_comp->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2c->adap.timeout = 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) i2c->adap.retries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) i2c->clk_main = devm_clk_get(&pdev->dev, "main");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (IS_ERR(i2c->clk_main)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_err(&pdev->dev, "cannot get main clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return PTR_ERR(i2c->clk_main);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (IS_ERR(i2c->clk_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dev_err(&pdev->dev, "cannot get dma clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return PTR_ERR(i2c->clk_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) i2c->clk_arb = devm_clk_get(&pdev->dev, "arb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (IS_ERR(i2c->clk_arb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) i2c->clk_arb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) clk = i2c->clk_main;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (i2c->have_pmic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (IS_ERR(i2c->clk_pmic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(&pdev->dev, "cannot get pmic clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return PTR_ERR(i2c->clk_pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) clk = i2c->clk_pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev_err(&pdev->dev, "Failed to set the speed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (i2c->dev_comp->max_dma_support > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = dma_set_mask(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(&pdev->dev, "dma_set_mask return error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ret = mtk_i2c_clock_enable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(&pdev->dev, "clock enable failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) mtk_i2c_init_hw(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) mtk_i2c_clock_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) I2C_DRV_NAME, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "Request I2C IRQ %d fail\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int mtk_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct mtk_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int mtk_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct mtk_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) i2c_mark_adapter_suspended(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int mtk_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct mtk_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = mtk_i2c_clock_enable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_err(dev, "clock enable failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) mtk_i2c_init_hw(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) mtk_i2c_clock_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) i2c_mark_adapter_resumed(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const struct dev_pm_ops mtk_i2c_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) mtk_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static struct platform_driver mtk_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .probe = mtk_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .remove = mtk_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .name = I2C_DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .pm = &mtk_i2c_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .of_match_table = of_match_ptr(mtk_i2c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) module_platform_driver(mtk_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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