^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * (C) Copyright 2003-2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This is a combined i2c adapter and algorithm driver for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * MPC107/Tsi107 PowerPC northbridge and processors that include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the same I2C unit (8240, 8245, 85xx).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Release 0.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mpc85xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRV_NAME "mpc-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPC_I2C_CLOCK_LEGACY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPC_I2C_CLOCK_PRESERVE (~0U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPC_I2C_FDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPC_I2C_CR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPC_I2C_SR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPC_I2C_DR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPC_I2C_DFSRR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCR_MEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCR_MIEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCR_MSTA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCR_MTX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCR_TXAK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCR_RSTA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CCR_RSVD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSR_MCF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSR_MAAS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSR_MBB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSR_MAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CSR_SRW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSR_MIF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSR_RXAK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct mpc_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) wait_queue_head_t queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 real_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 fdr, dfsrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool has_errata_A004447;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mpc_i2c_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u16 divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u16 fdr; /* including dfsrr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mpc_i2c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline void writeccr(struct mpc_i2c *i2c, u32 x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writeb(x, i2c->base + MPC_I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mpc_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Read again to allow register to stabilise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writeb(0, i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) wake_up(&i2c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * the bus, because it wants to send ACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Following sequence of enabling/disabling and sending start/stop generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * the 9 pulses, each with a START then ending with STOP, so it's all OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void mpc_i2c_fixup(struct mpc_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (k = 9; k; k--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writeccr(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) readb(i2c->base + MPC_I2C_DR); /* init xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) udelay(15); /* let it hit the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) local_irq_save(flags); /* should not be delayed further */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (k != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writeccr(i2c, CCR_MEN); /* Initiate STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) udelay(15); /* Let STOP propagate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writeccr(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!i2c->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (time_after(jiffies, orig_jiffies + timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_dbg(i2c->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writeccr(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cmd_err = readb(i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writeb(0, i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) result = wait_event_timeout(i2c->queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (i2c->interrupt & CSR_MIF), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (unlikely(!(i2c->interrupt & CSR_MIF))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_dbg(i2c->dev, "wait timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writeccr(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cmd_err = i2c->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) i2c->interrupt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!(cmd_err & CSR_MCF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_dbg(i2c->dev, "unfinished\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (cmd_err & CSR_MAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(i2c->dev, "MAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (writing && (cmd_err & CSR_RXAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(i2c->dev, "No RXAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* generate stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeccr(i2c, CCR_MEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __iomem *addr = i2c->base + MPC_I2C_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return readb_poll_timeout(addr, val, val & mask, 0, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Workaround for Erratum A004447. From the P2040CE Rev Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 1. Set up the frequency divider and sampling rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 2. I2CCR - a0h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 3. Poll for I2CSR[MBB] to get set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 4. If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * step 5. If MAL is not set, then go to step 13.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 5. I2CCR - 00h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 6. I2CCR - 22h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 7. I2CCR - a2h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 8. Poll for I2CSR[MBB] to get set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 9. Issue read to I2CDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * 10. Poll for I2CSR[MIF] to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 11. I2CCR - 82h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 12. Workaround complete. Skip the next steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 13. Issue read to I2CDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * 14. Poll for I2CSR[MIF] to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * 15. I2CCR - 80h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writeccr(i2c, CCR_MEN | CCR_MSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val = readb(i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (val & CSR_MAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writeccr(i2c, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writeccr(i2c, CCR_MSTA | CCR_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writeccr(i2c, CCR_MEN | CCR_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writeccr(i2c, CCR_MEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 *real_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct mpc_i2c_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int pvr = mfspr(SPRN_PVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (clock == MPC_I2C_CLOCK_LEGACY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* see below - default fdr = 0x3f -> div = 2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Determine divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) divider = mpc5xxx_get_bus_frequency(node) / clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * We want to choose an FDR/DFSR that generates an I2C bus speed that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * is equal to or lower than the requested speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) div = &mpc_i2c_dividers_52xx[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Old MPC5200 rev A CPUs do not support the high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (div->fdr & 0xc0 && pvr == 0x80822011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (div->divider >= divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return (int)div->fdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void mpc_i2c_setup_52xx(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret, fdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (clock == MPC_I2C_CLOCK_PRESERVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_dbg(i2c->dev, "using fdr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) readb(i2c->base + MPC_I2C_FDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void mpc_i2c_setup_52xx(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_PPC_MPC512x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void mpc_i2c_setup_512x(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct device_node *node_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) const u32 *pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Enable I2C interrupts for mpc5121 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) node_ctrl = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "fsl,mpc5121-i2c-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (node_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctrl = of_iomap(node_ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pval = of_get_property(node, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) idx = (*pval & 0xff) / 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) setbits32(ctrl, 1 << (24 + idx * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) iounmap(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) of_node_put(node_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* The clock setup for the 52xx works also fine for the 512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mpc_i2c_setup_52xx(node, i2c, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #else /* CONFIG_PPC_MPC512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void mpc_i2c_setup_512x(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif /* CONFIG_PPC_MPC512x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_FSL_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {49152, 0x011e}, {61440, 0x011f}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static u32 mpc_i2c_get_sec_cfg_8xxx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) node = of_find_node_by_name(NULL, "global-utilities");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const u32 *prop = of_get_property(node, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Map and check POR Device Status Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * (PORDEVSR2) at 0xE0014. Note than while MPC8533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * and MPC8544 indicate SEC frequency ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * configuration as bit 26 in PORDEVSR2, other MPC8xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * parts may store it differently or may not have it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "Error: couldn't map PORDEVSR2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val = in_be32(reg) & 0x00000020; /* sec-cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static u32 mpc_i2c_get_prescaler_8xxx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * may have prescaler 1, 2, or 3, depending on the power-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* mpc85xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) || pvr_version_is(PVR_VER_E500MC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) || pvr_version_is(PVR_VER_E5500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) || pvr_version_is(PVR_VER_E6500)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int svr = mfspr(SPRN_SVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((SVR_SOC_VER(svr) == SVR_8540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) || (SVR_SOC_VER(svr) == SVR_8541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) || (SVR_SOC_VER(svr) == SVR_8560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) || (SVR_SOC_VER(svr) == SVR_8555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) || (SVR_SOC_VER(svr) == SVR_8610))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* the above 85xx SoCs have prescaler 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) else if ((SVR_SOC_VER(svr) == SVR_8533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) || (SVR_SOC_VER(svr) == SVR_8544))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* the above 85xx SoCs have prescaler 3 or 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* all the other 85xx have prescaler 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) prescaler = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 *real_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) const struct mpc_i2c_divider *div = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 prescaler = mpc_i2c_get_prescaler_8xxx();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (clock == MPC_I2C_CLOCK_LEGACY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) divider = fsl_get_sys_freq() / clock / prescaler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fsl_get_sys_freq(), clock, divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * We want to choose an FDR/DFSR that generates an I2C bus speed that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * is equal to or lower than the requested speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) div = &mpc_i2c_dividers_8xxx[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (div->divider >= divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return div ? (int)div->fdr : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void mpc_i2c_setup_8xxx(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret, fdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (clock == MPC_I2C_CLOCK_PRESERVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) readb(i2c->base + MPC_I2C_DFSRR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) readb(i2c->base + MPC_I2C_FDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) i2c->real_clk, fdr >> 8, fdr & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #else /* !CONFIG_FSL_SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void mpc_i2c_setup_8xxx(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct mpc_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #endif /* CONFIG_FSL_SOC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void mpc_i2c_start(struct mpc_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Clear arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writeb(0, i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Start with MEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) writeccr(i2c, CCR_MEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static void mpc_i2c_stop(struct mpc_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) writeccr(i2c, CCR_MEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int mpc_write(struct mpc_i2c *i2c, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) const u8 *data, int length, int restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int i, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned timeout = i2c->adap.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 flags = restart ? CCR_RSTA : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Start as master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Write target byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writeb((target << 1), i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) result = i2c_wait(i2c, timeout, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Write data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writeb(data[i], i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) result = i2c_wait(i2c, timeout, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int mpc_read(struct mpc_i2c *i2c, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u8 *data, int length, int restart, bool recv_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned timeout = i2c->adap.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 flags = restart ? CCR_RSTA : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Switch to read - restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Write target address byte - this time with the read flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) result = i2c_wait(i2c, timeout, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (length == 1 && !recv_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) result = i2c_wait(i2c, timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * For block reads, we have to know the total length (1st byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * before we can determine if we are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (i || !recv_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Generate txack on next to last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (i == length - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) | CCR_TXAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Do not generate stop on last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (i == length - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) | CCR_MTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) byte = readb(i2c->base + MPC_I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Adjust length if first received byte is length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * The length is 1 length byte plus actually data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (i == 0 && recv_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) length += byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * For block reads, generate txack here if data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * is 1 byte (total length is 2 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (length == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) | CCR_TXAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) data[i] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct mpc_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mpc_i2c_start(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Allow bus up to 1s to become not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (signal_pending(current)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(i2c->dev, "Interrupted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writeccr(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (time_after(jiffies, orig_jiffies + HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 status = readb(i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_dbg(i2c->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writeb(status & ~CSR_MAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) i2c_recover_bus(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (i = 0; ret >= 0 && i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_dbg(i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pmsg->flags & I2C_M_RD ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pmsg->len, pmsg->addr, i + 1, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (pmsg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) recv_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (recv_len && ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pmsg->len = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mpc_i2c_stop(i2c); /* Initiate STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Wait until STOP is seen, allow up to 1 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (time_after(jiffies, orig_jiffies + HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 status = readb(i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(i2c->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writeb(status & ~CSR_MAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) i2c->base + MPC_I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) i2c_recover_bus(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return (ret < 0) ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static u32 mpc_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct mpc_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (i2c->has_errata_A004447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mpc_i2c_fixup_A004447(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mpc_i2c_fixup(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const struct i2c_algorithm mpc_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .master_xfer = mpc_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .functionality = mpc_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct i2c_adapter mpc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .algo = &mpc_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .timeout = HZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .recover_bus = fsl_i2c_bus_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct of_device_id mpc_i2c_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int fsl_i2c_probe(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct mpc_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const u32 *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 clock = MPC_I2C_CLOCK_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int plen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) match = of_match_device(mpc_i2c_of_match, &op->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) i2c->dev = &op->dev; /* for debug and error output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) init_waitqueue_head(&i2c->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) i2c->base = of_iomap(op->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!i2c->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(i2c->dev, "failed to map controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto fail_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (i2c->irq) { /* no i2c->irq implies polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) result = request_irq(i2c->irq, mpc_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) IRQF_SHARED, "i2c-mpc", i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(i2c->dev, "failed to attach interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto fail_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * enable clock for the I2C peripheral (non fatal),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * keep a reference upon successful allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) clk = devm_clk_get(&op->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) err = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(&op->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto fail_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) i2c->clk_per = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) clock = MPC_I2C_CLOCK_PRESERVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) prop = of_get_property(op->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) &plen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (prop && plen == sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) clock = *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const struct mpc_i2c_data *data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) data->setup(op->dev.of_node, i2c, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* Backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (of_get_property(op->dev.of_node, "dfsrr", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (prop && plen == sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mpc_ops.timeout = *prop * HZ / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (mpc_ops.timeout < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mpc_ops.timeout = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) platform_set_drvdata(op, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i2c->has_errata_A004447 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) i2c->adap = mpc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) of_address_to_resource(op->dev.of_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "MPC adapter at 0x%llx", (unsigned long long)res.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) i2c->adap.dev.parent = &op->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) result = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto fail_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) fail_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (i2c->clk_per)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) clk_disable_unprepare(i2c->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) free_irq(i2c->irq, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) fail_request:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) irq_dispose_mapping(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) iounmap(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) fail_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) kfree(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int fsl_i2c_remove(struct platform_device *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct mpc_i2c *i2c = platform_get_drvdata(op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (i2c->clk_per)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) clk_disable_unprepare(i2c->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (i2c->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) free_irq(i2c->irq, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) irq_dispose_mapping(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) iounmap(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) kfree(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int mpc_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct mpc_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int mpc_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct mpc_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MPC_I2C_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct mpc_i2c_data mpc_i2c_data_512x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .setup = mpc_i2c_setup_512x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const struct mpc_i2c_data mpc_i2c_data_52xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .setup = mpc_i2c_setup_52xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const struct mpc_i2c_data mpc_i2c_data_8313 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .setup = mpc_i2c_setup_8xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const struct mpc_i2c_data mpc_i2c_data_8543 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .setup = mpc_i2c_setup_8xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const struct mpc_i2c_data mpc_i2c_data_8544 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .setup = mpc_i2c_setup_8xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct of_device_id mpc_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {.compatible = "fsl-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* Structure for a device driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct platform_driver mpc_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .probe = fsl_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .remove = fsl_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .of_match_table = mpc_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .pm = MPC_I2C_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) module_platform_driver(mpc_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "MPC824x/83xx/85xx/86xx/512x/52xx processors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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