^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 1. Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2. Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 3. Neither the names of the copyright holders nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * contributors may be used to endorse or promote products derived from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Alternatively, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * GNU General Public License ("GPL") version 2 as published by the Free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* General defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MLXCPLD_I2C_BUS_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MLXCPLD_I2C_DATA_REG_SZ 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MLXCPLD_I2C_MAX_ADDR_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MLXCPLD_I2C_RETR_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MLXCPLD_I2C_XFER_TO 500000 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MLXCPLD_I2C_POLL_TIME 2000 /* usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* LPC I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MLXCPLD_LPCI2C_CPBLTY_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MLXCPLD_LPCI2C_CTRL_REG 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MLXCPLD_LPCI2C_CMD_REG 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MLXCPLD_LPCI2C_STATUS_REG 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MLXCPLD_LPCI2C_DATA_REG 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* LPC I2C masks and parametres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MLXCPLD_LPCI2C_TRANS_END 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MLXCPLD_LPCI2C_STATUS_NACK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MLXCPLD_LPCI2C_NO_IND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MLXCPLD_LPCI2C_ACK_IND 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MLXCPLD_LPCI2C_NACK_IND 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mlxcpld_i2c_curr_xfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mlxcpld_i2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct mlxcpld_i2c_curr_xfer xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool smbus_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) for (i = 0; i < len - len % 4; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outl(*(u32 *)(data + i), addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (; i < len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) outb(*(data + i), addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 0; i < len - len % 4; i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *(u32 *)(data + i) = inl(addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) for (; i < len; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *(data + i) = inb(addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 *data, u8 datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 addr = priv->base_addr + offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) switch (datalen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *(data) = inb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *((u16 *)data) = inw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *((u16 *)data) = inw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *(data + 2) = inb(addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *((u32 *)data) = inl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 *data, u8 datalen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 addr = priv->base_addr + offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) switch (datalen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) outb(*(data), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outw(*((u16 *)data), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outw(*((u16 *)data), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) outb(*(data + 2), addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) outl(*((u32 *)data), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Check validity of received i2c messages parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Returns 0 if OK, other - in case of invalid parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_err(priv->dev, "Incorrect 0 num of messages\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (unlikely(msgs[0].addr > 0x7f)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(priv->dev, "Invalid address 0x%03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) msgs[0].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) for (i = 0; i < num; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (unlikely(!msgs[i].buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(priv->dev, "Invalid buf in msg[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (unlikely(msgs[0].addr != msgs[i].addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(priv->dev, "Invalid addr in msg[%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Check if transfer is completed and status of operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Returns 0 - transfer completed (both ACK or NACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * negative - transfer isn't finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (val & MLXCPLD_LPCI2C_TRANS_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (val & MLXCPLD_LPCI2C_STATUS_NACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * The slave is unable to accept the data. No such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * slave, command not understood, or unable to accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * any more data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *status = MLXCPLD_LPCI2C_NACK_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *status = MLXCPLD_LPCI2C_ACK_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *status = MLXCPLD_LPCI2C_NO_IND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct i2c_msg *msgs, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 comm_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) priv->xfer.msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) priv->xfer.msg_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * All upper layers currently are never use transfer with more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * 2 messages. Actually, it's also not so relevant in Mellanox systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * because of HW limitation. Max size of transfer is not more than 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * or 68 bytes in the current x86 LPCI2C bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv->xfer.addr_width = msgs[0].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->xfer.data_len = comm_len - priv->xfer.addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) priv->xfer.addr_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->xfer.data_len = comm_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Reset CPLD LPCI2C block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Make sure the CPLD is ready to start transmitting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (val & MLXCPLD_LPCI2C_TRANS_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!mlxcpld_i2c_check_busy(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) timeout += MLXCPLD_I2C_POLL_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } while (timeout <= MLXCPLD_I2C_XFER_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (timeout > MLXCPLD_I2C_XFER_TO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Wait for master transfer to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * It puts current process to sleep until we get interrupt or timeout expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Returns the number of transferred or read bytes or error (<0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int status, i, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u8 datalen, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!mlxcpld_i2c_check_status(priv, &status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) timeout += MLXCPLD_I2C_POLL_TIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case MLXCPLD_LPCI2C_NO_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case MLXCPLD_LPCI2C_ACK_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (priv->xfer.cmd != I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return (priv->xfer.addr_width + priv->xfer.data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (priv->xfer.msg_num == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!priv->xfer.msg[i].buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Actual read data len will be always the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * requested len. 0xff (line pull-up) will be returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * if slave has no data to return. Thus don't read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD. Only in case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * SMBus block read transaction data len can be different,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * check this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &datalen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(priv->dev, "Incorrect smbus block read message len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) datalen = priv->xfer.data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) priv->xfer.msg[i].buf, datalen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case MLXCPLD_LPCI2C_NACK_IND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int i, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u8 cmd, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &priv->xfer.data_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val = priv->xfer.addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Notify HW about SMBus block read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->xfer.msg[1].len == 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (priv->xfer.msg[1].flags & I2C_M_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; i < priv->xfer.msg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Don't write to CPLD buffer in read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) len, priv->xfer.msg[i].buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) priv->xfer.msg[i].len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) len += priv->xfer.msg[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Set target slave address with command for master transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * It should be latest executed function before CPLD transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Generic lpc-i2c transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Returns the number of processed messages or error (<0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 comm_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(priv->dev, "Incorrect message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (i = 0; i < num; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) comm_len += msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Check bus state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (mlxcpld_i2c_wait_for_free(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(priv->dev, "LPCI2C bridge is busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Usually it means something serious has happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * We can not have unfinished previous transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * so it doesn't make any sense to try to stop it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Probably we were not able to recover from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * previous error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * The only reasonable thing - is soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mlxcpld_i2c_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (mlxcpld_i2c_check_busy(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Do real transfer. Can't fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mlxcpld_i2c_xfer_msg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Wait for transaction complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) err = mlxcpld_i2c_wait_for_tc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return err < 0 ? err : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (priv->smbus_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct i2c_algorithm mlxcpld_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .master_xfer = mlxcpld_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .functionality = mlxcpld_i2c_func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .max_comb_1st_msg_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .flags = I2C_AQ_COMB_WRITE_THEN_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .max_comb_1st_msg_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct i2c_adapter mlxcpld_i2c_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = "i2c-mlxcpld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .algo = &mlxcpld_i2c_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .quirks = &mlxcpld_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .retries = MLXCPLD_I2C_RETR_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .nr = MLXCPLD_I2C_BUS_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int mlxcpld_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct mlxcpld_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Register with i2c layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Read capability register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Check support for extended transaction length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Check support for smbus block transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) priv->smbus_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (pdev->id >= -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mlxcpld_i2c_adapter.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) priv->adap = mlxcpld_i2c_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) priv->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) err = i2c_add_numbered_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int mlxcpld_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct platform_driver mlxcpld_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .probe = mlxcpld_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .remove = mlxcpld_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = MLXCPLD_I2C_DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) module_platform_driver(mlxcpld_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_ALIAS("platform:i2c-mlxcpld");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags