^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mellanox BlueField I2C bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Mellanox Technologies, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Defines what functionality is present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MLXBF_I2C_FUNC_SMBUS_BLOCK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MLXBF_I2C_FUNC_SMBUS_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) I2C_FUNC_SMBUS_PROC_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MLXBF_I2C_FUNC_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MLXBF_I2C_SMBUS_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Shared resources info in BlueField platforms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MLXBF_I2C_COALESCE_TYU_SIZE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MLXBF_I2C_GPIO_TYU_SIZE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MLXBF_I2C_COREPLL_TYU_SIZE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MLXBF_I2C_COREPLL_YU_SIZE 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MLXBF_I2C_SHARED_RES_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * refer to their respective offsets relative to the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * memory-mapped region whose addresses are specified in either the DT or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * the ACPI tables or above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * SMBus Master core clock frequency. Timing configurations are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * strongly dependent on the core clock frequency of the SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Master. Default value is set to 400MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Reference clock for Bluefield - 156 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MLXBF_I2C_PLL_IN_FREQ (156 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Constant used to determine the PLL frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MLNXBF_I2C_COREPLL_CONST 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* PLL registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MLXBF_I2C_CORE_PLL_REG0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MLXBF_I2C_CORE_PLL_REG1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MLXBF_I2C_CORE_PLL_REG2 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* OR cause register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MLXBF_I2C_CAUSE_OR_CLEAR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Arbiter Cause Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MLXBF_I2C_CAUSE_ARBITER 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Cause Status flags. Note that those bits might be considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * as interrupt enabled bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Transaction ended with STOP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Master arbitration lost. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Unexpected start detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Unexpected stop detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Wait for transfer continuation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Failed to generate STOP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Failed to generate START. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Clock toggle completed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Transfer timeout occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Master busy bit reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MLXBF_I2C_CAUSE_UNEXPECTED_START | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MLXBF_I2C_CAUSE_PUT_START_FAILED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MLXBF_I2C_CAUSE_M_FW_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Slave cause status flags. Note that those bits might be considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * as interrupt enabled bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Write transaction received successfully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Read transaction received, waiting for response. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Slave busy bit reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MLXBF_I2C_CAUSE_SLAVE_ARBITER_BITS_MASK GENMASK(20, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Cause coalesce registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MLXBF_I2C_CAUSE_COALESCE_0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MLXBF_I2C_CAUSE_COALESCE_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MLXBF_I2C_CAUSE_COALESCE_2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT MLXBF_I2C_SMBUS_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Functional enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Force OE enable register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * SDA/SCL lines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * SMBUS GW0 -> bits[26:25]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * SMBUS GW1 -> bits[28:27]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * SMBUS GW2 -> bits[30:29]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Note that gw_id can be 0,1 or 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* SMBus timing parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MLXBF_I2C_TIMING_100KHZ = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MLXBF_I2C_TIMING_400KHZ = 400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MLXBF_I2C_TIMING_1000KHZ = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Defines SMBus operating frequency and core clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * According to ADB files, default values are compliant to 100KHz SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @ 400MHz core clock. The driver should be able to calculate core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * frequency based on PLL parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Core PLL TYU configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Core PLL YU configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Core PLL frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static u64 mlxbf_i2c_corepll_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* SMBus Master GW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MLXBF_I2C_SMBUS_MASTER_GW 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Number of bytes received and sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MLXBF_I2C_SMBUS_RS_BYTES 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Packet error check (PEC) value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MLXBF_I2C_SMBUS_MASTER_PEC 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Status bits (ACK/NACK/FW Timeout). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MLXBF_I2C_SMBUS_MASTER_STATUS 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* SMbus Master Finite State Machine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MLXBF_I2C_SMBUS_MASTER_FSM 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * When enabled, the master will issue a stop condition in case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * timeout while waiting for FW response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MLXBF_I2C_SMBUS_EN_FW_TIMEOUT 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MLXBF_I2C_MASTER_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MLXBF_I2C_MASTER_START_BIT | MLXBF_I2C_MASTER_STOP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MLXBF_I2C_MASTER_ENABLE_WRITE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MLXBF_I2C_MASTER_ENABLE_READ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Parse expected bytes shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* SMBus master GW Data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Maximum bytes to read/write per SMBus transaction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* All bytes were transmitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* NACK received. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Slave's byte count >128 bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Timeout occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MLXBF_I2C_SMBUS_STATUS_READ_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* SMBus slave GW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MLXBF_I2C_SMBUS_SLAVE_GW 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Number of bytes received and sent from/to master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Packet error check (PEC) value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MLXBF_I2C_SMBUS_SLAVE_PEC 0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* SMBus slave Finite State Machine (FSM). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MLXBF_I2C_SMBUS_SLAVE_FSM 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Should be set when all raised causes handled, and cleared by HW on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * every new cause.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MLXBF_I2C_SMBUS_SLAVE_READY 0x52c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MLXBF_I2C_SLAVE_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* SMBus slave GW Data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* SMbus slave configuration registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MLXBF_I2C_SLAVE_ADDR_ENABLED(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ((addr) & (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Timeout is given in microsends. Note also that timeout handling is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * exact.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Encapsulates timing parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mlxbf_i2c_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 scl_high; /* Clock high period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 scl_low; /* Clock low period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 sda_rise; /* Data rise time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 sda_fall; /* Data fall time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 scl_rise; /* Clock rise time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 scl_fall; /* Clock fall time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 hold_start; /* Hold time after (REPEATED) START. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 hold_data; /* Data hold time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 setup_start; /* REPEATED START condition setup time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u16 setup_stop; /* STOP condition setup time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u16 setup_data; /* Data setup time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 pad; /* Padding. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u16 buf; /* Bus free time between STOP and START. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u16 thigh_max; /* Thigh max. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 timeout; /* Detect clock low timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MLXBF_I2C_F_READ = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MLXBF_I2C_F_WRITE = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MLXBF_I2C_F_NORESTART = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MLXBF_I2C_F_SMBUS_OPERATION = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MLXBF_I2C_F_SMBUS_BLOCK = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MLXBF_I2C_F_SMBUS_PEC = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct mlxbf_i2c_smbus_operation {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 length; /* Buffer length in bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MLXBF_I2C_SMBUS_OP_CNT_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MLXBF_I2C_SMBUS_OP_CNT_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MLXBF_I2C_SMBUS_OP_CNT_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mlxbf_i2c_smbus_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u8 operation_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct mlxbf_i2c_resource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void __iomem *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* List of chip resources that are being accessed by the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MLXBF_I2C_SMBUS_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MLXBF_I2C_MST_CAUSE_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MLXBF_I2C_SLV_CAUSE_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MLXBF_I2C_COALESCE_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MLXBF_I2C_COREPLL_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MLXBF_I2C_GPIO_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MLXBF_I2C_END_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Helper macro to define an I2C resource parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MLXBF_I2C_RES_PARAMS(addr, size, str) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .start = (addr), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .end = (addr) + (size) - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = (str) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct resource mlxbf_i2c_coalesce_tyu_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MLXBF_I2C_COALESCE_TYU_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "COALESCE_MEM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct resource mlxbf_i2c_corepll_tyu_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MLXBF_I2C_COREPLL_TYU_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "COREPLL_MEM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct resource mlxbf_i2c_corepll_yu_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MLXBF_I2C_COREPLL_YU_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "COREPLL_MEM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct resource mlxbf_i2c_gpio_tyu_params =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MLXBF_I2C_GPIO_TYU_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "GPIO_MEM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct mutex mlxbf_i2c_coalesce_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct mutex mlxbf_i2c_corepll_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct mutex mlxbf_i2c_gpio_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Mellanox BlueField chip type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum mlxbf_i2c_chip_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MLXBF_I2C_CHIP_TYPE_2, /* Mallanox BlueField-2 chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct mlxbf_i2c_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) enum mlxbf_i2c_chip_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Chip shared resources that are being used by the I2C controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Callback to calculate the core PLL frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mlxbf_i2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct mlxbf_i2c_chip_info *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mlxbf_i2c_resource *smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct mlxbf_i2c_resource *mst_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct mlxbf_i2c_resource *slv_cause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct mlxbf_i2c_resource *coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u64 frequency; /* Core frequency in Hz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int bus; /* Physical bus identifier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [MLXBF_I2C_CHIP_TYPE_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .params = &mlxbf_i2c_coalesce_tyu_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .lock = &mlxbf_i2c_coalesce_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .type = MLXBF_I2C_COALESCE_RES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [MLXBF_I2C_CHIP_TYPE_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .params = &mlxbf_i2c_corepll_tyu_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .lock = &mlxbf_i2c_corepll_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .type = MLXBF_I2C_COREPLL_RES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [MLXBF_I2C_CHIP_TYPE_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .params = &mlxbf_i2c_corepll_yu_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .lock = &mlxbf_i2c_corepll_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .type = MLXBF_I2C_COREPLL_RES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [MLXBF_I2C_CHIP_TYPE_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .params = &mlxbf_i2c_gpio_tyu_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .lock = &mlxbf_i2c_gpio_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .type = MLXBF_I2C_GPIO_RES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static u8 mlxbf_i2c_bus_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct mutex mlxbf_i2c_bus_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Polling frequency in microseconds. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MLXBF_I2C_POLL_FREQ_IN_USEC 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MLXBF_I2C_SHIFT_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MLXBF_I2C_SHIFT_8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MLXBF_I2C_SHIFT_16 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MLXBF_I2C_SHIFT_24 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MLXBF_I2C_MASK_8 GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MLXBF_I2C_MASK_16 GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MLXBF_I2C_FREQUENCY_1GHZ 1000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Function to poll a set of bits at a specific address; it checks whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * the bits are equal to zero when eq_zero is set to 'true', and not equal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * to zero when eq_zero is set to 'false'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * Note that the timeout is given in microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static u32 mlxbf_smbus_poll(void __iomem *io, u32 addr, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) bool eq_zero, u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) timeout = (timeout / MLXBF_I2C_POLL_FREQ_IN_USEC) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bits = readl(io + addr) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (eq_zero ? bits == 0 : bits != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return eq_zero ? 1 : bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) udelay(MLXBF_I2C_POLL_FREQ_IN_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } while (timeout-- != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * SW must make sure that the SMBus Master GW is idle before starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * a transaction. Accordingly, this function polls the Master FSM stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * bit; it returns false when the bit is asserted, true if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static bool mlxbf_smbus_master_wait_for_idle(struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 mask = MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 addr = MLXBF_I2C_SMBUS_MASTER_FSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 timeout = MLXBF_I2C_SMBUS_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (mlxbf_smbus_poll(priv->smbus->io, addr, mask, true, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static bool mlxbf_i2c_smbus_transaction_success(u32 master_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 cause_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * When transaction ended with STOP, all bytes were transmitted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * and no NACK received, then the transaction ended successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * On the other hand, when the GW is configured with the stop bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * de-asserted then the SMBus expects the following GW configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * for transfer continuation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Poll SMBus master status and return transaction status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * i.e. whether succeeded or failed. I2C and SMBus fault codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * are returned as negative numbers from most calls, with zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * or some positive number indicating a non-fault return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 master_status_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 cause_status_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * GW busy bit is raised by the driver and cleared by the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * when the transaction is completed. The busy bit is a good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * indicator of transaction status. So poll the busy bit, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * then read the cause and master status bits to determine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * errors occurred during the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mlxbf_smbus_poll(priv->smbus->io, MLXBF_I2C_SMBUS_MASTER_GW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MLXBF_I2C_MASTER_BUSY_BIT, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MLXBF_I2C_SMBUS_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Read cause status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cause_status_bits = readl(priv->mst_cause->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MLXBF_I2C_CAUSE_ARBITER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * Parse both Cause and Master GW bits, then return transaction status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) master_status_bits = readl(priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MLXBF_I2C_SMBUS_MASTER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (mlxbf_i2c_smbus_transaction_success(master_status_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cause_status_bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * In case of timeout on GW busy, the ISR will clear busy bit but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * transaction ended bits cause will not be set so the transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * fails. Then, we must check Master GW status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MLXBF_I2C_CAUSE_M_GW_BUSY_FALL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) const u8 *data, u8 length, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 offset, aligned_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) aligned_length = round_up(length, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Copy data bytes from 4-byte aligned source buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Data copied to the Master GW Data Descriptor MUST be shifted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * left so the data starts at the MSB of the descriptor registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * as required by the underlying hardware. Enable byte swapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * when writing data bytes to the 32 * 32-bit HW Data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * a.k.a Master GW Data Descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (offset = 0; offset < aligned_length; offset += sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) data32 = *((u32 *)(data + offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) iowrite32be(data32, priv->smbus->io + addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 *data, u8 length, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 data32, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u8 byte, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mask = sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Data bytes in the Master GW Data Descriptor are shifted left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * so the data starts at the MSB of the descriptor registers as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * set by the underlying hardware. Enable byte swapping while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * reading data bytes from the 32 * 32-bit HW Data registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * a.k.a Master GW Data Descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) data32 = ioread32be(priv->smbus->io + addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *((u32 *)(data + offset)) = data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!(length & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) data32 = ioread32be(priv->smbus->io + addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) for (byte = 0; byte < (length & mask); byte++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) data[offset + byte] = data32 & GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) data32 = ror32(data32, MLXBF_I2C_SHIFT_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u8 len, u8 block_en, u8 pec_en, bool read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Set Master GW control word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) command = MLXBF_I2C_MASTER_ENABLE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) command = MLXBF_I2C_MASTER_ENABLE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Clear status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Set the cause data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel(~0x0, priv->smbus->io + MLXBF_I2C_CAUSE_OR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Zero PEC byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Zero byte count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_RS_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* GW activation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(command, priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_GW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Poll master status and check status bits. An ACK is sent when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * completing writing data to the bus (Master 'byte_count_done' bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * is set to 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return mlxbf_i2c_smbus_check_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct mlxbf_i2c_smbus_request *request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u8 op_idx, data_idx, data_len, write_len, read_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct mlxbf_i2c_smbus_operation *operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 read_en, write_en, block_en, pec_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u8 slave, flags, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u8 *read_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) read_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) data_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) read_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) write_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) write_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) read_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) block_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pec_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) slave = request->slave & GENMASK(6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) addr = slave << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* First of all, check whether the HW is idle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (WARN_ON(!mlxbf_smbus_master_wait_for_idle(priv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Set first byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) data_desc[data_idx++] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) operation = &request->operation[op_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) flags = operation->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * Note that read and write operations might be handled by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * then write command byte and set the optional SMBus specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * bits such as block_en and pec_en. These bits MUST be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * submitted by the first operation only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pec_en = flags & MLXBF_I2C_F_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (flags & MLXBF_I2C_F_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) write_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) write_len += operation->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) memcpy(data_desc + data_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) operation->buffer, operation->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) data_idx += operation->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * We assume that read operations are performed only once per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * SMBus transaction. *TBD* protect this statement so it won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * be executed twice? or return an error if we try to read more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * than once?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (flags & MLXBF_I2C_F_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) read_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Subtract 1 as required by HW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) read_len = operation->length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) read_buf = operation->buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Set Master GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) data_len = write_len + 1; /* Add one byte of the slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Note that data_len cannot be 0. Indeed, the slave address byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * must be written to the data registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MLXBF_I2C_MASTER_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (write_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pec_en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (read_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Write slave address to Master GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) MLXBF_I2C_MASTER_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pec_en, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Get Master GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) MLXBF_I2C_MASTER_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Get data from Master GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) memcpy(read_buf, data_desc, read_len + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * After a read operation the SMBus FSM ps (present state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * needs to be 'manually' reset. This should be removed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * next tag integration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) priv->smbus->io + MLXBF_I2C_SMBUS_MASTER_FSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* I2C SMBus protocols. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u8 read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) request->operation[0].length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) request->operation[0].flags = MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u8 *data, bool read, bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) request->operation[0].length += pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) request->operation[0].flags |= read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) request->operation[0].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u8 *command, u8 *data, bool read, bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) request->operation[1].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) request->operation[1].length += pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) request->operation[1].flags = read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) request->operation[1].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u8 *command, u8 *data, bool read, bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) request->operation[1].length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) request->operation[1].length += pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) request->operation[1].flags = read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) request->operation[1].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u8 *command, u8 *data, u8 *data_len, bool read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * As specified in the standard, the max number of bytes to read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * per block operation is 32 bytes. In Golan code, the controller can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * read up to 128 bytes and write up to 127 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) request->operation[1].length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) request->operation[1].flags = read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Skip the first data byte, which corresponds to the number of bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * to read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) request->operation[1].buffer = data + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *data_len = request->operation[1].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Set the number of byte to read. This will be used by userspace. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) data[0] = *data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u8 *command, u8 *data, u8 *data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) bool read, bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) request->operation[1].length =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) request->operation[1].flags = read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) request->operation[1].buffer = data + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) *data_len = request->operation[1].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Set the number of bytes to read. This will be used by userspace. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) data[0] = *data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u8 *command, u8 *data, bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) request->operation[1].length = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) request->operation[1].flags = MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) request->operation[1].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) request->operation[2].length = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) request->operation[2].flags = MLXBF_I2C_F_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) request->operation[2].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u8 *command, u8 *data, u8 *data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bool pec_check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) request->operation[0].length = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) request->operation[0].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) request->operation[0].buffer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) I2C_SMBUS_BLOCK_MAX : *data_len + pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) request->operation[1].length = length - pec_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) request->operation[1].flags = MLXBF_I2C_F_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) request->operation[1].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) request->operation[2].length = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) request->operation[2].flags = MLXBF_I2C_F_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) request->operation[2].buffer = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) *data_len = length; /* including PEC byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Initialization functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return priv->chip->type == type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static struct mlxbf_i2c_resource *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const struct mlxbf_i2c_chip_info *chip = priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct mlxbf_i2c_resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u8 res_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) res = chip->shared_res[res_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (res && res->type == type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int mlxbf_i2c_init_resource(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct mlxbf_i2c_resource **res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct mlxbf_i2c_resource *tmp_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!res || *res || type >= MLXBF_I2C_END_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!tmp_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) tmp_res->params = platform_get_resource(pdev, IORESOURCE_MEM, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!tmp_res->params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) devm_kfree(dev, tmp_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) tmp_res->io = devm_ioremap_resource(dev, tmp_res->params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (IS_ERR(tmp_res->io)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) devm_kfree(dev, tmp_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return PTR_ERR(tmp_res->io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) tmp_res->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) *res = tmp_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) bool minimum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u64 frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * Compute ticks as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * Ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) frequency = priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * The number of ticks is rounded down and if minimum is equal to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * then add one tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (minimum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ticks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 mask, u8 shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) const struct mlxbf_i2c_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) u32 timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) timer = mlxbf_i2c_set_timer(priv, timings->scl_high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) false, MLXBF_I2C_MASK_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) timer |= mlxbf_i2c_set_timer(priv, timings->scl_low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) false, MLXBF_I2C_MASK_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) MLXBF_I2C_SHIFT_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) writel(timer, priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) writel(timer, priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_THOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) writel(timer, priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) timer = mlxbf_i2c_set_timer(priv, timings->buf, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) timer = timings->timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) writel(timer, priv->smbus->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) enum mlxbf_i2c_timings_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MLXBF_I2C_TIMING_CONFIG_100KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) MLXBF_I2C_TIMING_CONFIG_400KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MLXBF_I2C_TIMING_CONFIG_1000KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Note that the mlxbf_i2c_timings->timeout value is not related to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * bus frequency, it is impacted by the time it takes the driver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * complete data transmission before transaction abort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [MLXBF_I2C_TIMING_CONFIG_100KHZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .scl_high = 4810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .scl_low = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .hold_start = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .setup_start = 4800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .setup_stop = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .setup_data = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .sda_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .sda_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .scl_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .scl_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .hold_data = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .buf = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .thigh_max = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .timeout = 106500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [MLXBF_I2C_TIMING_CONFIG_400KHZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .scl_high = 1011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .scl_low = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .hold_start = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .setup_start = 700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .setup_stop = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .setup_data = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .sda_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .sda_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .scl_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .scl_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .hold_data = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .buf = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .thigh_max = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .timeout = 106500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .scl_high = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .scl_low = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .hold_start = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .setup_start = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .setup_stop = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .setup_data = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .sda_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .sda_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .scl_rise = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .scl_fall = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .hold_data = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .buf = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .thigh_max = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .timeout = 106500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int mlxbf_i2c_init_timings(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) enum mlxbf_i2c_timings_config config_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u32 config_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) config_khz = MLXBF_I2C_TIMING_100KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) switch (config_khz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Default settings is 100 KHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pr_warn("Illegal value %d: defaulting to 100 KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) config_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case MLXBF_I2C_TIMING_100KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) case MLXBF_I2C_TIMING_400KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) case MLXBF_I2C_TIMING_1000KHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int mlxbf_i2c_get_gpio(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct mlxbf_i2c_resource *gpio_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (!gpio_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * The GPIO region in TYU space is shared among I2C busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * This function MUST be serialized to avoid racing when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * claiming the memory region and/or setting up the GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) lockdep_assert_held(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Check whether the memory map exist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (gpio_res->io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) params = gpio_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) size = resource_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!devm_request_mem_region(dev, params->start, size, params->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) gpio_res->io = devm_ioremap(dev, params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (!gpio_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) devm_release_mem_region(dev, params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int mlxbf_i2c_release_gpio(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct mlxbf_i2c_resource *gpio_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!gpio_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mutex_lock(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (gpio_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* Release the GPIO resource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) params = gpio_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) devm_iounmap(dev, gpio_res->io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) devm_release_mem_region(dev, params->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) resource_size(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) mutex_unlock(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int mlxbf_i2c_get_corepll(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct mlxbf_i2c_resource *corepll_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) corepll_res = mlxbf_i2c_get_shared_resource(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) MLXBF_I2C_COREPLL_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (!corepll_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * The COREPLL region in TYU space is shared among I2C busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * This function MUST be serialized to avoid racing when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * claiming the memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) lockdep_assert_held(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Check whether the memory map exist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (corepll_res->io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) params = corepll_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) size = resource_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!devm_request_mem_region(dev, params->start, size, params->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) corepll_res->io = devm_ioremap(dev, params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (!corepll_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) devm_release_mem_region(dev, params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int mlxbf_i2c_release_corepll(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct mlxbf_i2c_resource *corepll_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) corepll_res = mlxbf_i2c_get_shared_resource(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MLXBF_I2C_COREPLL_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mutex_lock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (corepll_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Release the CorePLL resource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) params = corepll_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) devm_iounmap(dev, corepll_res->io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) devm_release_mem_region(dev, params->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) resource_size(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) mutex_unlock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int mlxbf_i2c_init_master(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) struct mlxbf_i2c_resource *gpio_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) u32 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* This configuration is only needed for BlueField 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!gpio_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * The GPIO region in TYU space is shared among I2C busses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * This function MUST be serialized to avoid racing when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * claiming the memory region and/or setting up the GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_lock(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ret = mlxbf_i2c_get_gpio(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(dev, "Failed to get gpio resource");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mutex_unlock(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * TYU - Configuration for GPIO pins. Those pins must be asserted in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * instead of HW_OE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * For now, we do not reset the GPIO state when the driver is removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * First, it is not necessary to disable the bus since we are using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * the same busses. Then, some busses might be shared among Linux and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * platform firmware; disabling the bus might compromise the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) config_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) mutex_unlock(gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static u64 mlxbf_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) u64 core_frequency, pad_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u8 core_od, core_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 corepll_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) u16 core_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* Get Core PLL configuration bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) core_f = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_F_TYU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) MLXBF_I2C_COREPLL_CORE_F_TYU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) core_od = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_OD_TYU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) core_r = rol32(corepll_val, MLXBF_I2C_COREPLL_CORE_R_TYU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) MLXBF_I2C_COREPLL_CORE_R_TYU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * Compute PLL output frequency as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) * CORE_F + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * (CORE_R + 1) * (CORE_OD + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * and PadFrequency, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) core_frequency = pad_frequency * (++core_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) core_frequency /= (++core_r) * (++core_od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return core_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static u64 mlxbf_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) u32 corepll_reg1_val, corepll_reg2_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) u64 corepll_frequency, pad_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) u8 core_od, core_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) u32 core_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) pad_frequency = MLXBF_I2C_PLL_IN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* Get Core PLL configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) core_f = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_F_YU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) MLXBF_I2C_COREPLL_CORE_F_YU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) core_r = rol32(corepll_reg1_val, MLXBF_I2C_COREPLL_CORE_R_YU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) MLXBF_I2C_COREPLL_CORE_R_YU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) core_od = rol32(corepll_reg2_val, MLXBF_I2C_COREPLL_CORE_OD_YU_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) MLXBF_I2C_COREPLL_CORE_OD_YU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * Compute PLL output frequency as follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * CORE_F / 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * PLL_OUT_FREQ = PLL_IN_FREQ * ----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * (CORE_R + 1) * (CORE_OD + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * and PadFrequency, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) corepll_frequency = (pad_frequency * core_f) / MLNXBF_I2C_COREPLL_CONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) corepll_frequency /= (++core_r) * (++core_od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return corepll_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) const struct mlxbf_i2c_chip_info *chip = priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct mlxbf_i2c_resource *corepll_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) u64 *freq = &priv->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) corepll_res = mlxbf_i2c_get_shared_resource(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) MLXBF_I2C_COREPLL_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (!corepll_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * First, check whether the TYU core Clock frequency is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * The TYU core frequency is the same for all I2C busses; when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * the first device gets probed the frequency is determined and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * stored into a globally visible variable. So, first of all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * check whether the frequency is already set. Here, we assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * that the frequency is expected to be greater than 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) mutex_lock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (!mlxbf_i2c_corepll_frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (!chip->calculate_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mutex_unlock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = mlxbf_i2c_get_corepll(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) dev_err(dev, "Failed to get corePLL resource");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) mutex_unlock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mutex_unlock(corepll_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) *freq = mlxbf_i2c_corepll_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static int mlxbf_slave_enable(struct mlxbf_i2c_priv *priv, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u32 slave_reg, slave_reg_tmp, slave_reg_avail, slave_addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u8 reg, reg_cnt, byte, addr_tmp, reg_avail, byte_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) bool avail, disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) avail = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * Read the slave registers. There are 4 * 32-bit slave registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * Each slave register can hold up to 4 * 8-bit slave configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) for (reg = 0; reg < reg_cnt; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) slave_reg = readl(priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * Each register holds 4 slave addresses. So, we have to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * the byte order consistent with the value read in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * update the register correctly, if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) slave_reg_tmp = slave_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) for (byte = 0; byte < 4; byte++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) addr_tmp = slave_reg_tmp & GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * Mark the first available slave address slot, i.e. its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * enabled bit should be unset. This slot might be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * later on to register our slave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (!avail && !MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) reg_avail = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) byte_avail = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) slave_reg_avail = slave_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * Parse slave address bytes and check whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) * slave address already exists and it's enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) * i.e. most significant bit is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if ((addr_tmp & slave_addr_mask) == addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (MLXBF_I2C_SLAVE_ADDR_ENABLED(addr_tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* Parse next byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) slave_reg_tmp >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* Exit the loop if the slave address is found. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (!avail && !disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return -EINVAL; /* No room for a new slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (avail && !disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) reg = reg_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) byte = byte_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* Set the slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) slave_reg_avail &= ~(slave_addr_mask << (byte * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) slave_reg_avail |= addr << (byte * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) slave_reg = slave_reg_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* Enable the slave address and update the register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) slave_reg |= (1 << MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT) << (byte * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) reg * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static int mlxbf_slave_disable(struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) u32 slave_reg, slave_reg_tmp, slave_addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) u8 addr, addr_tmp, reg, reg_cnt, slave_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct i2c_client *client = priv->slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) bool exist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) exist = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) slave_addr_mask = MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * Read the slave registers. There are 4 * 32-bit slave registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) * Each slave register can hold up to 4 * 8-bit slave configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * (7-bit address, 1 status bit (1 if enabled, 0 if not)).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) for (reg = 0; reg < reg_cnt; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) slave_reg = readl(priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* Check whether the address slots are empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (slave_reg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Each register holds 4 slave addresses. So, we have to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * the byte order consistent with the value read in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * update the register correctly, if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) slave_reg_tmp = slave_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) slave_byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) while (slave_reg_tmp != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) addr_tmp = slave_reg_tmp & slave_addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * Parse slave address bytes and check whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * slave address already exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (addr_tmp == addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) exist = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /* Parse next byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) slave_reg_tmp >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) slave_byte += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* Exit the loop if the slave address is found. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (exist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (!exist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return 0; /* Slave is not registered, nothing to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Cleanup the slave address slot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) slave_reg &= ~(GENMASK(7, 0) << (slave_byte * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) writel(slave_reg, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) reg * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static int mlxbf_i2c_init_coalesce(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct mlxbf_i2c_resource *coalesce_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) * Unlike BlueField-1 platform, the coalesce registers is a dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * resource in the next generations of BlueField.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) coalesce_res = mlxbf_i2c_get_shared_resource(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) MLXBF_I2C_COALESCE_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (!coalesce_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * The Cause Coalesce group in TYU space is shared among
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * I2C busses. This function MUST be serialized to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) * racing when claiming the memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) lockdep_assert_held(mlxbf_i2c_gpio_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* Check whether the memory map exist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (coalesce_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) priv->coalesce = coalesce_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) params = coalesce_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) size = resource_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (!request_mem_region(params->start, size, params->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) coalesce_res->io = ioremap(params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (!coalesce_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) release_mem_region(params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) priv->coalesce = coalesce_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) MLXBF_I2C_COALESCE_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static int mlxbf_i2c_release_coalesce(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct mlxbf_i2c_resource *coalesce_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) coalesce_res = priv->coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (coalesce_res->io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) params = coalesce_res->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) size = resource_size(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) mutex_lock(coalesce_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) iounmap(coalesce_res->io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) release_mem_region(params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) mutex_unlock(coalesce_res->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) devm_release_mem_region(dev, params->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static int mlxbf_i2c_init_slave(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u32 int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /* Reset FSM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) writel(0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_FSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * Enable slave cause interrupt bits. Drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * masters issue a Read and Write, respectively. But, clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * interrupts first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Finally, set the 'ready' bit to start handling transactions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* Initialize the cause coalesce resource. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ret = mlxbf_i2c_init_coalesce(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) dev_err(dev, "failed to initialize cause coalesce\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) bool *write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) const struct mlxbf_i2c_chip_info *chip = priv->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u32 coalesce0_reg, cause_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) u8 slave_shift, is_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) *write = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) *read = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) MLXBF_I2C_CAUSE_YU_SLAVE_BIT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) is_set = coalesce0_reg & (1 << slave_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (!is_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Check the source of the interrupt, i.e. whether a Read or Write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) *read = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) *write = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* Clear cause bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static bool mlxbf_smbus_slave_wait_for_idle(struct mlxbf_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) u32 timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) u32 mask = MLXBF_I2C_CAUSE_S_GW_BUSY_FALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) u32 addr = MLXBF_I2C_CAUSE_ARBITER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (mlxbf_smbus_poll(priv->slv_cause->io, addr, mask, false, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* Send byte to 'external' smbus master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static int mlxbf_smbus_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) u8 write_size, pec_en, addr, byte, value, byte_cnt, desc_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) struct i2c_client *slave = priv->slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) u32 control32, data32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) byte = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) desc_size = MLXBF_I2C_SLAVE_DATA_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * Read bytes received from the external master. These bytes should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) * be located in the first data descriptor register of the slave GW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * These bytes are the slave address byte and the internal register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * address, if supplied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (recv_bytes > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) data32 = ioread32be(priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* Parse the received bytes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) switch (recv_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) byte = (data32 >> 8) & GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) addr = (data32 & GENMASK(7, 0)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Check whether it's our slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (slave->addr != addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * I2C read transactions may start by a WRITE followed by a READ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * Indeed, most slave devices would expect the internal address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * following the slave address byte. So, write that byte first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * and then, send the requested data bytes to the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (recv_bytes > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) value = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) * Now, send data to the master; currently, the driver supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * READ_BYTE, READ_WORD and BLOCK READ protocols. Note that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * hardware can send up to 128 bytes per transfer. That is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * size of its data registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) for (byte_cnt = 0; byte_cnt < desc_size; byte_cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) data_desc[byte_cnt] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* Send a stop condition to the backend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Handle the actual transfer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* Set the number of bytes to write to master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) write_size = (byte_cnt - 1) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* Write data to Slave GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) pec_en = 0; /* Disable PEC since it is not supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* Prepare control word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) control32 = MLXBF_I2C_SLAVE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) writel(control32, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_GW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * Wait until the transfer is completed; the driver will wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * until the GW is idle, a cause will rise on fall of GW busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) mlxbf_smbus_slave_wait_for_idle(priv, MLXBF_I2C_SMBUS_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* Release the Slave GW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* Receive bytes from 'external' smbus master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static int mlxbf_smbus_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct i2c_client *slave = priv->slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u8 value, byte, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* Read data from Slave GW data descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) MLXBF_I2C_SLAVE_DATA_DESC_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* Check whether its our slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) addr = data_desc[0] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (slave->addr != addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * Notify the slave backend; another I2C master wants to write data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * to us. This event is sent once the slave address and the write bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* Send the received data to the slave backend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) for (byte = 1; byte < recv_bytes; byte++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) value = data_desc[byte];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* Send a stop condition to the backend. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* Release the Slave GW. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) writel(0x0, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_PEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) writel(0x1, priv->smbus->io + MLXBF_I2C_SMBUS_SLAVE_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static irqreturn_t mlxbf_smbus_irq(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) struct mlxbf_i2c_priv *priv = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) bool read, write, irq_is_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) u32 rw_bytes_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) u8 recv_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * Read TYU interrupt register and determine the source of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * interrupt. Based on the source of the interrupt one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * following actions are performed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * - Receive data and send response to master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * - Send data and release slave GW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * Handle read/write transaction only. CRmaster and Iarp requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * are ignored for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (!irq_is_set || (!read && !write)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* Nothing to do here, interrupt was not from this device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * bytes from/to master. These are defined by 8-bits each. If the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * 8 bits are set, then the master expect to read N bytes from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * slave, if the higher 8 bits are sent then the slave expect N bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * from the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) rw_bytes_reg = readl(priv->smbus->io +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * For now, the slave supports 128 bytes transfer. Discard remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * data bytes if the master wrote more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * data descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * Note that we will never expect to transfer more than 128 bytes; as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * specified in the SMBus standard, block transactions cannot exceed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * 32 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) mlxbf_smbus_irq_send(priv, recv_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) mlxbf_smbus_irq_recv(priv, recv_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct mlxbf_i2c_smbus_request request = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct mlxbf_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) bool read, pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) u8 byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) request.slave = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) read = (read_write == I2C_SMBUS_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) pec = flags & I2C_FUNC_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) mlxbf_i2c_smbus_quick_command(&request, read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) mlxbf_i2c_smbus_byte_func(&request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) read ? &data->byte : &command, read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) read ? "read" : "write", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) read, pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) read ? "read" : "write", command, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) mlxbf_i2c_smbus_data_word_func(&request, &command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) (u8 *)&data->word, read, pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) read ? "read" : "write", command, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) byte_cnt = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) &byte_cnt, read, pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) read ? "read" : "write", byte_cnt, command, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) mlxbf_i2c_smbus_block_func(&request, &command, data->block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) &byte_cnt, read, pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) read ? "read" : "write", byte_cnt, command, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) case I2C_FUNC_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) mlxbf_i2c_smbus_process_call_func(&request, &command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) (u8 *)&data->word, pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) command, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) case I2C_FUNC_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) byte_cnt = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) mlxbf_i2c_smbus_blk_process_call_func(&request, &command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) data->block, &byte_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) byte_cnt, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return mlxbf_i2c_smbus_start_transaction(priv, &request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (priv->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) * Do not support ten bit chip address and do not use Packet Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * Checking (PEC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ret = mlxbf_slave_enable(priv, slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) priv->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) WARN_ON(!priv->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /* Unregister slave, i.e. disable the slave address in hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ret = mlxbf_slave_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) priv->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return MLXBF_I2C_FUNC_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) [MLXBF_I2C_CHIP_TYPE_1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .type = MLXBF_I2C_CHIP_TYPE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .shared_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .calculate_freq = mlxbf_calculate_freq_from_tyu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) [MLXBF_I2C_CHIP_TYPE_2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .type = MLXBF_I2C_CHIP_TYPE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .shared_res = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .calculate_freq = mlxbf_calculate_freq_from_yu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static const struct i2c_algorithm mlxbf_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .smbus_xfer = mlxbf_i2c_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .functionality = mlxbf_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .reg_slave = mlxbf_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .unreg_slave = mlxbf_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static struct i2c_adapter_quirks mlxbf_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const struct of_device_id mlxbf_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .compatible = "mellanox,i2c-mlxbf1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .compatible = "mellanox,i2c-mlxbf2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .data = &mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) MODULE_DEVICE_TABLE(of, mlxbf_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) const struct acpi_device_id *aid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) unsigned long bus_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) const char *uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!aid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) uid = acpi_device_uid(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (!uid || !(*uid)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) dev_err(dev, "Cannot retrieve UID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ret = kstrtoul(uid, 0, &bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) priv->bus = bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static int mlxbf_i2c_of_probe(struct device *dev, struct mlxbf_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) const struct of_device_id *oid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) int bus_id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) oid = of_match_node(mlxbf_i2c_dt_ids, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!oid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) priv->chip = oid->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) bus_id = of_alias_get_id(dev->of_node, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (bus_id >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) priv->bus = bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (bus_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) dev_err(dev, "Cannot get bus id");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) return bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) static int mlxbf_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) struct mlxbf_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ret = mlxbf_i2c_acpi_probe(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (ret < 0 && ret != -ENOENT && ret != -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ret = mlxbf_i2c_of_probe(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ret = mlxbf_i2c_init_resource(pdev, &priv->smbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) MLXBF_I2C_SMBUS_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) dev_err(dev, "Cannot fetch smbus resource info");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) MLXBF_I2C_MST_CAUSE_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) dev_err(dev, "Cannot fetch cause master resource info");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) MLXBF_I2C_SLV_CAUSE_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) dev_err(dev, "Cannot fetch cause slave resource info");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) adap = &priv->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) adap->class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) adap->algo = &mlxbf_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) adap->quirks = &mlxbf_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) adap->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) adap->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) adap->nr = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) i2c_set_adapdata(adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) /* Read Core PLL frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) dev_err(dev, "cannot get core clock frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* Set to default value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) priv->frequency = MLXBF_I2C_COREPLL_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) * Initialize master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) * Note that a physical bus might be shared among Linux and firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) * (e.g., ATF). Thus, the bus should be initialized and ready and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * bus initialization would be unnecessary. This requires additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * knowledge about physical busses. But, since an extra initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) * does not really hurt, then keep the code as is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ret = mlxbf_i2c_init_master(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) dev_err(dev, "failed to initialize smbus master %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) priv->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) mlxbf_i2c_init_timings(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) mlxbf_i2c_init_slave(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ret = devm_request_irq(dev, irq, mlxbf_smbus_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) IRQF_ONESHOT | IRQF_SHARED | IRQF_PROBE_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) dev_err(dev, "Cannot get irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) priv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) mutex_lock(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) mlxbf_i2c_bus_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) mutex_unlock(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static int mlxbf_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) struct resource *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) params = priv->smbus->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) devm_release_mem_region(dev, params->start, resource_size(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) params = priv->mst_cause->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) devm_release_mem_region(dev, params->start, resource_size(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) params = priv->slv_cause->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) devm_release_mem_region(dev, params->start, resource_size(params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) * Release shared resources. This should be done when releasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) * the I2C controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) mutex_lock(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) if (--mlxbf_i2c_bus_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) mlxbf_i2c_release_coalesce(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) mlxbf_i2c_release_corepll(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) mlxbf_i2c_release_gpio(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) mutex_unlock(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) devm_free_irq(dev, priv->irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static struct platform_driver mlxbf_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .probe = mlxbf_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .remove = mlxbf_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .name = "i2c-mlxbf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .of_match_table = mlxbf_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static int __init mlxbf_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) mutex_init(&mlxbf_i2c_coalesce_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) mutex_init(&mlxbf_i2c_corepll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) mutex_init(&mlxbf_i2c_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) mutex_init(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) return platform_driver_register(&mlxbf_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) module_init(mlxbf_i2c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static void __exit mlxbf_i2c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) platform_driver_unregister(&mlxbf_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) mutex_destroy(&mlxbf_i2c_bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) mutex_destroy(&mlxbf_i2c_gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) mutex_destroy(&mlxbf_i2c_corepll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) mutex_destroy(&mlxbf_i2c_coalesce_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) module_exit(mlxbf_i2c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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