^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * I2C bus driver for Amlogic Meson SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Meson I2C register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_SLAVE_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_TOK_LIST0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_TOK_LIST1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_TOK_WDATA0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_TOK_WDATA1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_TOK_RDATA0 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_TOK_RDATA1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Control register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_CTRL_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_CTRL_ACK_IGNORE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_CTRL_STATUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_CTRL_ERROR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_CTRL_CLKDIV GENMASK(21, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_CTRL_CLKDIVEXT GENMASK(29, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_SLV_ADDR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_SLV_SDA_FILTER GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_SLV_SCL_FILTER GENMASK(13, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_SLV_SCL_LOW GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_SLV_SCL_LOW_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_TIMEOUT_MS 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FILTER_DELAY 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) TOKEN_END = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) TOKEN_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TOKEN_SLAVE_ADDR_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) TOKEN_SLAVE_ADDR_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) TOKEN_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) TOKEN_DATA_LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) TOKEN_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) STATE_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) STATE_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct meson_i2c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned char div_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * struct meson_i2c - Meson I2C device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @adap: I2C adapter instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @dev: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @regs: Base address of the device memory mapped registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @clk: Pointer to clock structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @msg: Pointer to the current I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @state: Current state in the driver state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @last: Flag set for the last message in the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @count: Number of bytes to be sent/received in current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @pos: Current position in the send/receive buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @error: Flag set when an error is received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @lock: To avoid race conditions between irq handler and xfer code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @done: Completion used to wait for transfer termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @tokens: Sequence of tokens to be written to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @num_tokens: Number of tokens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @data: Pointer to the controlller's platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct meson_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 tokens[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int num_tokens;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct meson_i2c_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) data = readl(i2c->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(data, i2c->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) i2c->tokens[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) i2c->tokens[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) i2c->num_tokens = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (i2c->num_tokens < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) i2c->num_tokens++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void meson_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long clk_rate = clk_get_rate(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) div = DIV_ROUND_UP(clk_rate, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) div -= FILTER_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) div = DIV_ROUND_UP(div, i2c->data->div_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* clock divider has 12 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (div > GENMASK(11, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(i2c->dev, "requested bus frequency too low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) div = GENMASK(11, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FIELD_PREP(REG_CTRL_CLKDIV, div & GENMASK(9, 0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FIELD_PREP(REG_CTRL_CLKDIVEXT, div >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Disable HIGH/LOW mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk_rate, freq, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 rdata0, rdata1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rdata0, rdata1, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (i = 0; i < min(4, len); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *buf++ = (rdata0 >> i * 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 4; i < min(8, len); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 wdata0 = 0, wdata1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < min(4, len); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) wdata0 |= *buf++ << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) for (i = 4; i < min(8, len); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) wdata1 |= *buf++ << ((i - 4) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(wdata0, i2c->regs + REG_TOK_WDATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(wdata1, i2c->regs + REG_TOK_WDATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) wdata0, wdata1, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bool write = !(i2c->msg->flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i2c->count = min(i2c->msg->len - i2c->pos, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < i2c->count - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) meson_i2c_add_token(i2c, TOKEN_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (i2c->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (write || i2c->pos + i2c->count < i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) meson_i2c_add_token(i2c, TOKEN_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) meson_i2c_add_token(i2c, TOKEN_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ctrl & REG_CTRL_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * The bit is set when the IGNORE_NAK bit is cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * and the device didn't respond. In this case, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * I2C controller automatically generates a STOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(i2c->dev, "error bit set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) i2c->error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (i2c->state == STATE_READ && i2c->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) i2c->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) i2c->pos += i2c->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (i2c->pos >= i2c->msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct meson_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_lock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) meson_i2c_reset_tokens(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ctrl = readl(i2c->regs + REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) i2c->state, i2c->pos, i2c->count, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (i2c->state == STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) meson_i2c_transfer_complete(i2c, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (i2c->state == STATE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) complete(&i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Restart the processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) meson_i2c_prepare_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int token;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) TOKEN_SLAVE_ADDR_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FIELD_PREP(REG_SLV_ADDR, msg->addr << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) meson_i2c_add_token(i2c, TOKEN_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) meson_i2c_add_token(i2c, token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int last, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) i2c->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i2c->last = last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i2c->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) i2c->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i2c->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) meson_i2c_reset_tokens(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!(msg->flags & I2C_M_NOSTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) meson_i2c_do_start(i2c, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) meson_i2c_prepare_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) reinit_completion(&i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (atomic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) !(ctrl & REG_CTRL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 10, I2C_TIMEOUT_MS * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) time_left = wait_for_completion_timeout(&i2c->done, time_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Protect access to i2c struct and registers from interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * handlers triggered by a transfer terminated after the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * timeout period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (atomic && !ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) meson_i2c_transfer_complete(i2c, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Abort any active operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (i2c->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = i2c->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int meson_i2c_xfer_messages(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct i2c_msg *msgs, int num, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct meson_i2c *i2c = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret ?: i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return meson_i2c_xfer_messages(adap, msgs, num, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int meson_i2c_xfer_atomic(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return meson_i2c_xfer_messages(adap, msgs, num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static u32 meson_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct i2c_algorithm meson_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .master_xfer = meson_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .master_xfer_atomic = meson_i2c_xfer_atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .functionality = meson_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int meson_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct meson_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct i2c_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) i2c_parse_fw_timings(&pdev->dev, &timings, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_lock_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) init_completion(&i2c->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) i2c->data = (const struct meson_i2c_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(&pdev->dev, "can't get device clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return PTR_ERR(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) i2c->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (IS_ERR(i2c->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return PTR_ERR(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(&pdev->dev, "can't request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(&pdev->dev, "can't prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) strlcpy(i2c->adap.name, "Meson I2C adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) i2c->adap.algo = &meson_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) i2c->adap.dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i2c->adap.algo_data = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * A transfer is triggered when START bit changes from 0 to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Ensure that the bit is set to 0 after probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Disable filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) REG_SLV_SDA_FILTER | REG_SLV_SCL_FILTER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) meson_i2c_set_clk_div(i2c, timings.bus_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int meson_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct meson_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct meson_i2c_data i2c_meson6_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .div_factor = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct meson_i2c_data i2c_gxbb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .div_factor = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const struct meson_i2c_data i2c_axg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .div_factor = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct of_device_id meson_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_DEVICE_TABLE(of, meson_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct platform_driver meson_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .probe = meson_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .remove = meson_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "meson-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .of_match_table = meson_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) module_platform_driver(meson_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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