^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Code portions referenced from the i2x-pxa and i2c-pnx drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Make SMBus byte and word transactions work on LPC178x/7x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Anton Protopopov, Emcraft Systems, antonp@emcraft.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* LPC24xx register offsets and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC24XX_I2CONSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC24XX_I2STAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC24XX_I2DAT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC24XX_I2ADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC24XX_I2SCLH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC24XX_I2SCLL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC24XX_I2CONCLR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC24XX_AA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC24XX_SI BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC24XX_STO BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC24XX_STA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC24XX_I2EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC24XX_STO_AA (LPC24XX_STO | LPC24XX_AA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC24XX_CLEAR_ALL (LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) LPC24XX_STA | LPC24XX_I2EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* I2C SCL clock has different duty cycle depending on mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_STD_MODE_DUTY 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_FAST_MODE_DUTY 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_FAST_MODE_PLUS_DUTY 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 26 possible I2C status codes, but codes applicable only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * to master are listed here and used in this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) M_BUS_ERROR = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) M_START = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) M_REPSTART = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MX_ADDR_W_ACK = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX_ADDR_W_NACK = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MX_DATA_W_ACK = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MX_DATA_W_NACK = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) M_DATA_ARB_LOST = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MR_ADDR_R_ACK = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MR_ADDR_R_NACK = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MR_DATA_R_ACK = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MR_DATA_R_NACK = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) M_I2C_IDLE = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct lpc2k_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int msg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Will force clear all statuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel(0, i2c->base + LPC24XX_I2ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * If the transfer needs to abort for some reason, we'll try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * force a stop condition to clear any pending bus conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Wait for status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Bus was not idle, try to reset adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) i2c_lpc2k_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * I2C in the LPC2xxx series is basically a state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Just run through the steps based on the current status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) status = readl(i2c->base + LPC24XX_I2STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case M_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case M_REPSTART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Start bit was just sent out, send out addr and dir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data = i2c_8bit_addr_from_msg(i2c->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(data, i2c->base + LPC24XX_I2DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case MX_ADDR_W_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case MX_DATA_W_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Address or data was sent out with an ACK. If there is more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * data to send, send it now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (i2c->msg_idx < i2c->msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(i2c->msg->buf[i2c->msg_idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) i2c->base + LPC24XX_I2DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else if (i2c->is_last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Last message, send stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) i2c->msg_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) i2c->msg_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case MR_ADDR_R_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Receive first byte from slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (i2c->msg->len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Last byte, return NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Not last byte, return ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case MR_DATA_R_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * The I2C shows NACK status on reads, so we need to accept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * the NACK as an ACK here. This should be ok, as the real
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * BACK would of been caught on the address write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case MR_DATA_R_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Data was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (i2c->msg_idx < i2c->msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) i2c->msg->buf[i2c->msg_idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) readl(i2c->base + LPC24XX_I2DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* If transfer is done, send STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i2c->msg_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Message is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (i2c->msg_idx >= i2c->msg->len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) i2c->msg_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * One pre-last data input, send NACK to tell the slave that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * this is going to be the last data byte to be transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (i2c->msg_idx >= i2c->msg->len - 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* One byte left to receive - NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* More than one byte left to receive - ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case MX_ADDR_W_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case MX_DATA_W_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case MR_ADDR_R_NACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* NACK processing is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) i2c->msg_status = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case M_DATA_ARB_LOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) i2c->msg_status = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Release the I2C bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Unexpected statuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) i2c->msg_status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Exit on failure or all bytes transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (i2c->msg_status != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) wake_up(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * If `msg_status` is zero, then `lpc2k_process_msg()`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * is responsible for clearing the SI flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (i2c->msg_status != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* A new transfer is kicked off by initiating a start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!msgidx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * A multi-message I2C transfer continues where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * previous I2C transfer left off and uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * current condition of the I2C adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) WARN_ON(i2c->msg->len == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (!(i2c->msg->flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Start transmit of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(i2c->msg->buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) i2c->base + LPC24XX_I2DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Start or repeated start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enable_irq(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Wait for transfer completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) msecs_to_jiffies(1000)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return i2c->msg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int msg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Check for bus idle condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) stat = readl(i2c->base + LPC24XX_I2STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (stat != M_I2C_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Something is holding the bus, try to clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return i2c_lpc2k_clear_arb(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Process a single message at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < msg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Save message pointer and current message data index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i2c->msg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i2c->msg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) i2c->msg_status = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) i2c->is_last = (i == (msg_num - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = lpc2k_process_msg(i2c, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct lpc2k_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) i2c_lpc2k_pump_msg(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Only emulated SMBus for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct i2c_algorithm i2c_lpc2k_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .master_xfer = i2c_lpc2k_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .functionality = i2c_lpc2k_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int i2c_lpc2k_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct lpc2k_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 scl_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) i2c->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (IS_ERR(i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return PTR_ERR(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (i2c->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) init_waitqueue_head(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(&pdev->dev, "error getting clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return PTR_ERR(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(&pdev->dev, "unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(&pdev->dev, "can't request interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto fail_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) disable_irq_nosync(i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Place controller is a known state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_lpc2k_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) &bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clkrate = clk_get_rate(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (clkrate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&pdev->dev, "can't get I2C base clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto fail_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Setup I2C dividers to generate clock with proper duty cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clkrate = clkrate / bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) else if (bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel(scl_high, i2c->base + LPC24XX_I2SCLH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) strlcpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) i2c->adap.algo = &i2c_lpc2k_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto fail_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_info(&pdev->dev, "LPC2K I2C adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fail_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int i2c_lpc2k_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int i2c_lpc2k_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int i2c_lpc2k_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) i2c_lpc2k_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .suspend_noirq = i2c_lpc2k_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .resume_noirq = i2c_lpc2k_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define I2C_LPC2K_DEV_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct of_device_id lpc2k_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .compatible = "nxp,lpc1788-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct platform_driver i2c_lpc2k_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .probe = i2c_lpc2k_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .remove = i2c_lpc2k_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "lpc2k-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .pm = I2C_LPC2K_DEV_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .of_match_table = lpc2k_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) module_platform_driver(i2c_lpc2k_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_ALIAS("platform:lpc2k-i2c");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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