^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ingenic JZ4780 I2C bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Imagination Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ4780_I2C_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ4780_I2C_TAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ4780_I2C_SAR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ4780_I2C_DC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ4780_I2C_SHCNT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ4780_I2C_SLCNT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ4780_I2C_FHCNT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ4780_I2C_FLCNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ4780_I2C_INTST 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ4780_I2C_INTM 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JZ4780_I2C_RXTL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JZ4780_I2C_TXTL 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JZ4780_I2C_CINTR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JZ4780_I2C_CRXUF 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JZ4780_I2C_CRXOF 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JZ4780_I2C_CTXOF 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JZ4780_I2C_CRXREQ 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JZ4780_I2C_CTXABRT 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define JZ4780_I2C_CRXDONE 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JZ4780_I2C_CACT 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JZ4780_I2C_CSTP 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define JZ4780_I2C_CSTT 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define JZ4780_I2C_CGC 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define JZ4780_I2C_ENB 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define JZ4780_I2C_STA 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define JZ4780_I2C_TXABRT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define JZ4780_I2C_DMACR 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define JZ4780_I2C_DMATDLR 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define JZ4780_I2C_DMARDLR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define JZ4780_I2C_SDASU 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define JZ4780_I2C_ACKGC 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define JZ4780_I2C_ENSTA 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define JZ4780_I2C_SDAHD 0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define X1000_I2C_SDAHD 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JZ4780_I2C_CTRL_STPHLD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define JZ4780_I2C_CTRL_SLVDIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define JZ4780_I2C_CTRL_REST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define JZ4780_I2C_CTRL_MATP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define JZ4780_I2C_CTRL_SATP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define JZ4780_I2C_CTRL_SPDF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define JZ4780_I2C_CTRL_SPDS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define JZ4780_I2C_CTRL_MD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define JZ4780_I2C_STA_SLVACT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define JZ4780_I2C_STA_MSTACT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define JZ4780_I2C_STA_RFF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define JZ4780_I2C_STA_RFNE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define JZ4780_I2C_STA_TFE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define JZ4780_I2C_STA_TFNF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define JZ4780_I2C_STA_ACT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define X1000_I2C_DC_STOP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define JZ4780_I2C_INTST_IGC BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define JZ4780_I2C_INTST_ISTT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define JZ4780_I2C_INTST_ISTP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define JZ4780_I2C_INTST_IACT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define JZ4780_I2C_INTST_RXDN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define JZ4780_I2C_INTST_TXABT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define JZ4780_I2C_INTST_RDREQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define JZ4780_I2C_INTST_TXEMP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define JZ4780_I2C_INTST_TXOF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define JZ4780_I2C_INTST_RXFL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define JZ4780_I2C_INTST_RXOF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define JZ4780_I2C_INTST_RXUF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define JZ4780_I2C_INTM_MIGC BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define JZ4780_I2C_INTM_MISTT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define JZ4780_I2C_INTM_MISTP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define JZ4780_I2C_INTM_MIACT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define JZ4780_I2C_INTM_MRXDN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define JZ4780_I2C_INTM_MTXABT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define JZ4780_I2C_INTM_MRDREQ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define JZ4780_I2C_INTM_MTXEMP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define JZ4780_I2C_INTM_MTXOF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define JZ4780_I2C_INTM_MRXFL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define JZ4780_I2C_INTM_MRXOF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define JZ4780_I2C_INTM_MRXUF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define JZ4780_I2C_DC_READ BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define JZ4780_I2C_SDAHD_HDENB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define JZ4780_I2C_ENB_I2C BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define JZ4780_I2C_FIFO_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define X1000_I2C_FIFO_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define JZ4780_I2C_TIMEOUT 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BUFSIZE 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum ingenic_i2c_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ID_JZ4780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ID_X1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* ingenic_i2c_config: SoC specific config data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct ingenic_i2c_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum ingenic_i2c_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int tx_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int rx_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct jz4780_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct ingenic_i2c_config *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* beginning of lock scope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned char *rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int rd_total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int rd_data_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int rd_cmd_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned char *wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int wt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int is_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int stop_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int data_buf[BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int cmd_buf[BUFSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* end of lock scope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct completion trans_waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return readw(i2c->iomem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long offset, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writew(val, i2c->iomem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int jz4780_i2c_disable(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned short regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long loops = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!(regval & JZ4780_I2C_ENB_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) usleep_range(5000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } while (--loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int jz4780_i2c_enable(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned short regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long loops = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (regval & JZ4780_I2C_ENB_I2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) usleep_range(5000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } while (--loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned short regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long loops = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if ((regval & JZ4780_I2C_STA_TFE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) !(regval & JZ4780_I2C_STA_MSTACT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) usleep_range(5000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } while (--loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (loops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(&i2c->adap.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "set device to address 0x%02x failed, STA=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) address, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int dev_clk_khz = clk_get_rate(i2c->clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int cnt_high = 0; /* HIGH period count of the SCL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int cnt_low = 0; /* LOW period count of the SCL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int cnt_period = 0; /* period count of the SCL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int setup_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int hold_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned short tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int i2c_clk = i2c->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (jz4780_i2c_disable(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_dbg(&i2c->adap.dev, "i2c not disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * fast mode, min LOW and HIGH period are 1300 ns and 600 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cnt_period = dev_clk_khz / i2c_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (i2c_clk <= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cnt_high = (cnt_period * 4000) / (4700 + 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cnt_high = (cnt_period * 600) / (1300 + 600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cnt_low = cnt_period - cnt_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * normal read are 2 messages, we cannot disable i2c controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * between these two messages, this means that we must always set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (i2c_clk <= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) JZ4780_I2CSHCNT_ADJUST(cnt_high));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) JZ4780_I2CSLCNT_ADJUST(cnt_low));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) JZ4780_I2CFHCNT_ADJUST(cnt_high));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) JZ4780_I2CFLCNT_ADJUST(cnt_low));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * a i2c device must internally provide a hold time at least 300ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * tHD:DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Standard Mode: min=300ns, max=3450ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Fast Mode: min=0ns, max=900ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * tSU:DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Standard Mode: min=250ns, max=infinite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Fast Mode: min=100(250ns is recommended), max=infinite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 1i2c_clk = 10^6 / dev_clk_khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * The actual hold time is (SDAHD + 1) * (i2c_clk period).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Length of setup time calculated using (SDASU - 1) * (ic_clk_period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (i2c_clk <= 100) { /* standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) setup_time = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) hold_time = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) setup_time = 450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) hold_time = 450;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (setup_time > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) setup_time = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (setup_time <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) setup_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (hold_time > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) hold_time = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (hold_time >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*i2c hold time enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (i2c->cdata->version >= ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, hold_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hold_time |= JZ4780_I2C_SDAHD_HDENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* disable hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (i2c->cdata->version >= ID_X1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* can send stop now if need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (i2c->cdata->version < ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tmp &= ~JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* disable all interrupts first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* then clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* then disable the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tmp &= ~JZ4780_I2C_ENB_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tmp |= JZ4780_I2C_ENB_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = jz4780_i2c_disable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&i2c->adap.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "unable to disable device during cleanup!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(&i2c->adap.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "device has interrupts after a complete cleanup!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int jz4780_i2c_prepare(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) jz4780_i2c_set_speed(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return jz4780_i2c_enable(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int cmd_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int cmd_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (i = 0; i < cmd_count - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if ((cmd_left == 0) && (i2c->cdata->version >= ID_X1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) jz4780_i2c_writew(i2c, JZ4780_I2C_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) JZ4780_I2C_DC_READ | X1000_I2C_DC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) complete(&i2c->trans_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned short intst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned short intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct jz4780_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) intst &= intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (intst & JZ4780_I2C_INTST_TXABT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) jz4780_i2c_trans_done(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (intst & JZ4780_I2C_INTST_RXOF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(&i2c->adap.dev, "received fifo overflow!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) jz4780_i2c_trans_done(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * When reading, always drain RX FIFO before we send more Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Commands to avoid fifo overrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (i2c->is_write == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int rd_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) & JZ4780_I2C_STA_RFNE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) i2c->rd_data_xfered++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (i2c->rd_data_xfered == i2c->rd_total_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) jz4780_i2c_trans_done(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) rd_left = i2c->rd_total_len - i2c->rd_data_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (rd_left <= i2c->cdata->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (intst & JZ4780_I2C_INTST_TXEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (i2c->is_write == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int max_send = (i2c->cdata->fifosize - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) - (i2c->rd_cmd_xfered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) - i2c->rd_data_xfered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int cmd_to_send = min(cmd_left, max_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (i2c->rd_cmd_xfered != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cmd_to_send = min(cmd_to_send,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) i2c->cdata->fifosize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) - i2c->cdata->tx_level - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (cmd_to_send) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) i2c->rd_cmd_xfered += cmd_to_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cmd_left = i2c->rd_total_len -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) i2c->rd_cmd_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) jz4780_i2c_send_rcmd(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cmd_to_send, cmd_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (cmd_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) intmsk &= ~JZ4780_I2C_INTM_MTXEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (i2c->cdata->version < ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) tmp = jz4780_i2c_readw(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) tmp &= ~JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) jz4780_i2c_writew(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned short data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned short i2c_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) while ((i2c_sta & JZ4780_I2C_STA_TFNF) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (i2c->wt_len > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) data = *i2c->wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) data &= ~JZ4780_I2C_DC_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if ((i2c->wt_len == 1) && (!i2c->stop_hold) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) (i2c->cdata->version >= ID_X1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) data |= X1000_I2C_DC_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) i2c->wbuf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i2c->wt_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (i2c->wt_len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if ((!i2c->stop_hold) && (i2c->cdata->version <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ID_X1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tmp = jz4780_i2c_readw(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tmp &= ~JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) jz4780_i2c_writew(i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) jz4780_i2c_trans_done(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned char *buf, int len, int cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) memset(buf, 0, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i2c->stop_hold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) i2c->is_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) i2c->rbuf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) i2c->rd_total_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) i2c->rd_data_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) i2c->rd_cmd_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (len <= i2c->cdata->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, i2c->cdata->rx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (i2c->cdata->version < ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tmp |= JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) timeout = wait_for_completion_timeout(&i2c->trans_waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) msecs_to_jiffies(wait_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(&i2c->adap.dev, "irq read timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) i2c->cmd, i2c->cmd_buf[i2c->cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) i2c->cmd, i2c->data_buf[i2c->cmd]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) jz4780_i2c_txabrt(i2c, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned char *buf, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int cnt, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int wait_time = JZ4780_I2C_TIMEOUT * (len + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (idx < (cnt - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) i2c->stop_hold = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) i2c->stop_hold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) i2c->is_write = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) i2c->wbuf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) i2c->wt_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) | JZ4780_I2C_INTM_MTXABT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (i2c->cdata->version < ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) tmp |= JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) timeout = wait_for_completion_timeout(&i2c->trans_waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) msecs_to_jiffies(wait_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (timeout && !i2c->stop_hold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned short i2c_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int write_in_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) timeout = JZ4780_I2C_TIMEOUT * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (; timeout > 0; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) !(i2c_sta & JZ4780_I2C_STA_TFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (!write_in_process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&i2c->adap.dev, "write wait timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) jz4780_i2c_txabrt(i2c, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int i = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct jz4780_i2c *i2c = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = jz4780_i2c_prepare(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&i2c->adap.dev, "I2C prepare failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = jz4780_i2c_set_target(i2c, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) for (i = 0; i < count; i++, msg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) count, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) count, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) jz4780_i2c_cleanup(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static u32 jz4780_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const struct i2c_algorithm jz4780_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .master_xfer = jz4780_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .functionality = jz4780_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const struct ingenic_i2c_config jz4780_i2c_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .version = ID_JZ4780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .fifosize = JZ4780_I2C_FIFO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .tx_level = JZ4780_I2C_FIFO_LEN / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .rx_level = JZ4780_I2C_FIFO_LEN / 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct ingenic_i2c_config x1000_i2c_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .version = ID_X1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .fifosize = X1000_I2C_FIFO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .tx_level = X1000_I2C_FIFO_LEN / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .rx_level = X1000_I2C_FIFO_LEN / 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const struct of_device_id jz4780_i2c_of_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { .compatible = "ingenic,jz4770-i2c", .data = &jz4780_i2c_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int jz4780_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) unsigned int clk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct jz4780_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) i2c->cdata = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!i2c->cdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(&pdev->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) i2c->adap.algo = &jz4780_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) i2c->adap.algo_data = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) i2c->adap.retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) sprintf(i2c->adap.name, "%s", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) init_completion(&i2c->trans_waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) spin_lock_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) i2c->iomem = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (IS_ERR(i2c->iomem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return PTR_ERR(i2c->iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (IS_ERR(i2c->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return PTR_ERR(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(&pdev->dev, "clock-frequency not specified in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) i2c->speed = clk_freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (i2c->speed == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(&pdev->dev, "clock-frequency minimum is 1000\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) jz4780_i2c_set_speed(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (i2c->cdata->version < ID_X1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) tmp &= ~JZ4780_I2C_CTRL_STPHLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2c->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int jz4780_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct jz4780_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static struct platform_driver jz4780_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .probe = jz4780_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .remove = jz4780_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .name = "jz4780-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .of_match_table = jz4780_i2c_of_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) module_platform_driver(jz4780_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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