^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright(c) 2012 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * GPL LICENSE SUMMARY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * it under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The full GNU General Public License is included in this distribution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * in the file called LICENSE.GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * BSD LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * modification, are permitted provided that the following conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * notice, this list of conditions and the following disclaimer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * * Neither the name of Intel Corporation nor the names of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * contributors may be used to endorse or promote products derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * S12xx Product Family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Features supported by this driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Hardware PEC yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Block buffer yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Block process call transaction no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Slave mode no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PCI Address Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SMBBAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Hardware Descriptor Constants - Control Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ISMT_DESC_I2C 0x20 /* I2C Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ISMT_DESC_INT 0x40 /* Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ISMT_DESC_SOE 0x80 /* Stop On Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Hardware Descriptor Constants - Status Field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ISMT_DESC_SCS 0x01 /* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ISMT_DESC_NAK 0x08 /* NAK Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ISMT_DESC_CRC 0x10 /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ISMT_DESC_COL 0x40 /* Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* iSMT General Register address offsets (SMBBAR + <addr>) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ISMT_GR_GCTRL 0x000 /* General Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ISMT_GR_ERRSTS 0x018 /* Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ISMT_GR_ERRINFO 0x01c /* Error Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* iSMT Master Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ISMT_MSTR_MSTS 0x10c /* Master Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* iSMT Miscellaneous Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* General Control Register (GCTRL) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ISMT_GCTRL_KILL 0x08 /* Kill */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Master Control Register (MCTRL) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Master Status Register (MSTS) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ISMT_MSTS_IP 0x01 /* In Progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Master Descriptor Size (MDS) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* SMBus PHY Global Timing Register (SPGT) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* MSI Control Register (MSICTL) bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* iSMT Hardware Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ismt_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 tgtaddr_rw; /* target address & r/w bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 wr_len_cmd; /* write length in bytes or a command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u8 rd_len; /* read length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 control; /* control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 status; /* status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 retry; /* collision retry and retry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 rxbytes; /* received bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 txbytes; /* transmitted bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 dptr_low; /* lower 32 bit of the data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 dptr_high; /* upper 32 bit of the data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ismt_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void __iomem *smba; /* PCI BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ismt_desc *hw; /* descriptor virt base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dma_addr_t io_rng_dma; /* descriptor HW base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 head; /* ring buffer head pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct completion cmp; /* interrupt completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct pci_device_id ismt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(pci, ismt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Bus speed control bits for slow debuggers - refer to the docs for usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned int bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) module_param(bus_speed, uint, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * __ismt_desc_dump() - dump the contents of a specific descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @dev: the iSMT device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @desc: the iSMT hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_dbg(dev, "Descriptor struct: %p\n", desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void ismt_desc_dump(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct device *dev = &priv->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct ismt_desc *desc = &priv->hw[priv->head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __ismt_desc_dump(dev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * ismt_gen_reg_dump() - dump the iSMT General Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void ismt_gen_reg_dump(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = &priv->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_dbg(dev, "Dump of the iSMT General Registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) priv->smba + ISMT_GR_GCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) readl(priv->smba + ISMT_GR_GCTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->smba + ISMT_GR_SMTICL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->smba + ISMT_GR_ERRINTMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) readl(priv->smba + ISMT_GR_ERRINTMSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) priv->smba + ISMT_GR_ERRAERMSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) readl(priv->smba + ISMT_GR_ERRAERMSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) priv->smba + ISMT_GR_ERRSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) readl(priv->smba + ISMT_GR_ERRSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) priv->smba + ISMT_GR_ERRINFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) readl(priv->smba + ISMT_GR_ERRINFO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * ismt_mstr_reg_dump() - dump the iSMT Master Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void ismt_mstr_reg_dump(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct device *dev = &priv->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(dev, "Dump of the iSMT Master Registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) priv->smba + ISMT_MSTR_MDBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->smba + ISMT_MSTR_MCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) readl(priv->smba + ISMT_MSTR_MCTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) priv->smba + ISMT_MSTR_MSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) readl(priv->smba + ISMT_MSTR_MSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) priv->smba + ISMT_MSTR_MDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) readl(priv->smba + ISMT_MSTR_MDS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) priv->smba + ISMT_MSTR_RPOLICY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) readl(priv->smba + ISMT_MSTR_RPOLICY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) priv->smba + ISMT_SPGT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) readl(priv->smba + ISMT_SPGT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * ismt_submit_desc() - add a descriptor to the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void ismt_submit_desc(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uint fmhp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) uint val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ismt_desc_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ismt_gen_reg_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ismt_mstr_reg_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Set the FMHP (Firmware Master Head Pointer)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val = readl(priv->smba + ISMT_MSTR_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) priv->smba + ISMT_MSTR_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Set the start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val = readl(priv->smba + ISMT_MSTR_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel(val | ISMT_MCTRL_SS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) priv->smba + ISMT_MSTR_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * ismt_process_desc() - handle the completion of the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @desc: the iSMT hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @data: data buffer from the upper layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @priv: ismt_priv struct holding our dma buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @size: SMBus transaction type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @read_write: flag to indicate if this is a read or write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ismt_process_desc(const struct ismt_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) union i2c_smbus_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ismt_priv *priv, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) char read_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __ismt_desc_dump(&priv->pci_dev->dev, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ismt_gen_reg_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ismt_mstr_reg_dump(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (desc->status & ISMT_DESC_SCS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (read_write == I2C_SMBUS_WRITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) size != I2C_SMBUS_PROC_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data->byte = dma_buffer[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) data->word = dma_buffer[0] | (dma_buffer[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (desc->rxbytes != dma_buffer[0] + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EMSGSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) memcpy(data->block, dma_buffer, desc->rxbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) memcpy(&data->block[1], dma_buffer, desc->rxbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) data->block[0] = desc->rxbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (likely(desc->status & ISMT_DESC_NAK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (desc->status & ISMT_DESC_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (desc->status & ISMT_DESC_COL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (desc->status & ISMT_DESC_LPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * ismt_access() - process an SMBus command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @adap: the i2c host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @addr: address of the i2c/SMBus target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * @flags: command options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * @read_write: read from or write to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @command: the i2c/SMBus command to issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @size: SMBus transaction type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * @data: read/write data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int ismt_access(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned short flags, char read_write, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dma_addr_t dma_addr = 0; /* address of the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 dma_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) enum dma_data_direction dma_direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct ismt_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ismt_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct device *dev = &priv->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) desc = &priv->hw[priv->head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Initialize the DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) memset(priv->buffer, 0, sizeof(priv->buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Initialize the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) memset(desc, 0, sizeof(struct ismt_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Initialize common control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (likely(pci_dev_msi_enabled(priv->pci_dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) desc->control = ISMT_DESC_FAIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) && (size != I2C_SMBUS_I2C_BLOCK_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) desc->control |= ISMT_DESC_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(dev, "I2C_SMBUS_QUICK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Send Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * The command field contains the write data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) desc->control |= ISMT_DESC_CWRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) desc->wr_len_cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Receive Byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dma_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) desc->rd_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Write Byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Command plus 1 data byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) desc->wr_len_cmd = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dma_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dma_direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dma_buffer[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dma_buffer[1] = data->byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Read Byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) desc->control |= ISMT_DESC_CWRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) desc->wr_len_cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) desc->rd_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dma_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Write Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) desc->wr_len_cmd = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dma_size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dma_direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dma_buffer[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dma_buffer[1] = data->word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dma_buffer[2] = data->word >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Read Word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) desc->wr_len_cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) desc->control |= ISMT_DESC_CWRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) desc->rd_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dma_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) desc->wr_len_cmd = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) desc->rd_len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dma_size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dma_direction = DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dma_buffer[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dma_buffer[1] = data->word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dma_buffer[2] = data->word >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Block Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dma_size = data->block[0] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dma_direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) desc->wr_len_cmd = dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) desc->control |= ISMT_DESC_BLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dma_buffer[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Block Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dma_size = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) desc->rd_len = dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) desc->wr_len_cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Make sure the length is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (data->block[0] < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) data->block[0] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) data->block[0] = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* i2c Block Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dma_size = data->block[0] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dma_direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) desc->wr_len_cmd = dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) desc->control |= ISMT_DESC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dma_buffer[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* i2c Block Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dma_size = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) desc->rd_len = dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) desc->wr_len_cmd = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * Per the "Table 15-15. I2C Commands",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * in the External Design Specification (EDS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * (Document Number: 508084, Revision: 2.0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * the _rw bit must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dev, "Unsupported transaction %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* map the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (dma_size != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(dev, " dev=%p\n", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_dbg(dev, " data=%p\n", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_dbg(dev, " dma_size=%d\n", dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_dbg(dev, " dma_direction=%d\n", dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dma_addr = dma_map_single(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dma_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dma_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (dma_mapping_error(dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev_err(dev, "Error in mapping dma buffer %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) desc->dptr_low = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) desc->dptr_high = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reinit_completion(&priv->cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Add the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ismt_submit_desc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Now we wait for interrupt completion, 1s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* unmap the data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (dma_size != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (unlikely(!time_left)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(dev, "completion wait timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* do any post processing of the descriptor here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = ismt_process_desc(desc, data, priv, size, read_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Update the ring pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) priv->head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) priv->head %= ISMT_DESC_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * ismt_func() - report which i2c commands are supported by this adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @adap: the i2c host adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static u32 ismt_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return I2C_FUNC_SMBUS_QUICK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) I2C_FUNC_SMBUS_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) I2C_FUNC_SMBUS_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) I2C_FUNC_SMBUS_I2C_BLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) I2C_FUNC_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .smbus_xfer = ismt_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .functionality = ismt_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * ismt_handle_isr() - interrupt handler bottom half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) complete(&priv->cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * ismt_do_interrupt() - IRQ interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * @vec: interrupt vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * @data: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static irqreturn_t ismt_do_interrupt(int vec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct ismt_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * check to see it's our interrupt, return IRQ_NONE if not ours
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * since we are sharing interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val = readl(priv->smba + ISMT_MSTR_MSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) priv->smba + ISMT_MSTR_MSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ismt_handle_isr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * ismt_do_msi_interrupt() - MSI interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @vec: interrupt vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * @data: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ismt_handle_isr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * ismt_hw_init() - initialize the iSMT hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void ismt_hw_init(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct device *dev = &priv->pci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* initialize the Master Descriptor Base Address (MDBA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* initialize the Master Control Register (MCTRL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* initialize the Master Status Register (MSTS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) writel(0, priv->smba + ISMT_MSTR_MSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* initialize the Master Descriptor Size (MDS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val = readl(priv->smba + ISMT_MSTR_MDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) priv->smba + ISMT_MSTR_MDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Set the SMBus speed (could use this for slow HW debuggers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val = readl(priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) switch (bus_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) case 80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case 400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case 1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val = readl(priv->smba + ISMT_SPGT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) switch (val & ISMT_SPGT_SPD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case ISMT_SPGT_SPD_80K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) bus_speed = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case ISMT_SPGT_SPD_100K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) bus_speed = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case ISMT_SPGT_SPD_400K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) bus_speed = 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case ISMT_SPGT_SPD_1M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) bus_speed = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * ismt_dev_init() - initialize the iSMT data structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int ismt_dev_init(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* allocate memory for the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) (ISMT_DESC_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * sizeof(struct ismt_desc)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &priv->io_rng_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!priv->hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) priv->head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) init_completion(&priv->cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * ismt_int_init() - initialize interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @priv: iSMT private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int ismt_int_init(struct ismt_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Try using MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) err = pci_enable_msi(priv->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) err = devm_request_irq(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) priv->pci_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ismt_do_msi_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "ismt-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_disable_msi(priv->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Try using legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) intx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_warn(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "Unable to use MSI interrupts, falling back to legacy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) err = devm_request_irq(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) priv->pci_dev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ismt_do_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "ismt-intx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static struct pci_driver ismt_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * ismt_probe() - probe for iSMT devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * @pdev: PCI-Express device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * @id: PCI-Express device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct ismt_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned long start, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pci_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) i2c_set_adapdata(&priv->adapter, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) priv->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) priv->adapter.class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) priv->adapter.algo = &smbus_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) priv->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) priv->adapter.retries = ISMT_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) priv->pci_dev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* enable bus mastering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Determine the address of the SMBus area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) start = pci_resource_start(pdev, SMBBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) len = pci_resource_len(pdev, SMBBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (!start || !len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "SMBus base address uninitialized, upgrade BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) snprintf(priv->adapter.name, sizeof(priv->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "SMBus iSMT adapter at %lx", start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev_err(&pdev->dev, "ACPI resource conflict!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "Failed to request SMBus region 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) start, start + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) priv->smba = pcim_iomap(pdev, SMBBAR, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!priv->smba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (pci_set_consistent_dma_mask(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DMA_BIT_MASK(32)) != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) err = ismt_dev_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ismt_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) err = ismt_int_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) err = i2c_add_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * ismt_remove() - release driver resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * @pdev: PCI-Express device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void ismt_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct ismt_priv *priv = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) i2c_del_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static struct pci_driver ismt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .name = "ismt_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .id_table = ismt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .probe = ismt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .remove = ismt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) module_pci_driver(ismt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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