^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - Based on i2c-piix4.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Philip Edelbrock <phil@netroedge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - Intel SCH support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Note: we assume there can only be one device, with one SMBus interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* SCH SMBus address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMBHSTCNT (0 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMBHSTSTS (1 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMBHSTCLK (2 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMBHSTADD (4 + sch_smba) /* TSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMBHSTCMD (5 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMBHSTDAT0 (6 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMBHSTDAT1 (7 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMBBLKDAT (0x20 + sch_smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_RETRIES 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* I2C constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCH_QUICK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCH_BYTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCH_BYTE_DATA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCH_WORD_DATA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCH_BLOCK_DATA 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned short sch_smba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct i2c_adapter sch_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int backbone_speed = 33000; /* backbone speed in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Start the i2c transaction -- the i2c_access will prepare the transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * and this function will execute it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * return 0 for success and others for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int sch_transaction(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) inb(SMBHSTDAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Make sure the SMBus host is ready to start transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) temp = inb(SMBHSTSTS) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Can not be busy since we checked it in sch_access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (temp & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dev_dbg(&sch_adapter.dev, "Completion (%02x). "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "Clear...\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (temp & 0x06) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "Resetting...\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) outb(temp, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) temp = inb(SMBHSTSTS) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(&sch_adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "SMBus is not ready: (%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* start the transaction by setting bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) temp = inb(SMBHSTSTS) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) } while ((temp & 0x08) && (retries++ < MAX_RETRIES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (retries > MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (temp & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "locked until next hard reset. (sorry!)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Clock stops and slave is stuck in mid-transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else if (temp & 0x02) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_err(&sch_adapter.dev, "Error: no response!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) } else if (temp & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_dbg(&sch_adapter.dev, "Post complete!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outb(temp, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) temp = inb(SMBHSTSTS) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (temp & 0x06) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Completion clear failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_dbg(&sch_adapter.dev, "Failed reset at end of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "transaction (%02x), Bus error!\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_dbg(&sch_adapter.dev, "No such address.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) inb(SMBHSTDAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This is the main access entry for i2c-sch access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * (0 for read and 1 for write), size is i2c transaction type and data is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * union of transaction for data to be transferred or data read from bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * return 0 for success and others for failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static s32 sch_access(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 command, int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int i, len, temp, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Make sure the SMBus host is not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) temp = inb(SMBHSTSTS) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (temp & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) temp = inw(SMBHSTCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * We can't determine if we have 33 or 25 MHz clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * SMBus, so expect 33 MHz and calculate a bus clock of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * 100 kHz. If we actually run at 25 MHz the bus will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * run ~75 kHz instead which should do no harm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_notice(&sch_adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "Clock divider uninitialized. Setting defaults\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outw(backbone_speed / (4 * 100), SMBHSTCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (read_write)?"READ":"WRITE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) outb((addr << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) size = SCH_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) outb((addr << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) outb(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) size = SCH_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) outb((addr << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) outb(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) outb(data->byte, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) size = SCH_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) outb((addr << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) outb(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) outb(data->word & 0xff, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) size = SCH_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) outb((addr << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) outb(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) outb(len, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 1; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) outb(data->block[i], SMBBLKDAT+i-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) size = SCH_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rc = sch_transaction();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (rc) /* Error in transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case SCH_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case SCH_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) data->byte = inb(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case SCH_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case SCH_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) data->block[0] = inb(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 1; i <= data->block[0]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) data->block[i] = inb(SMBBLKDAT+i-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static u32 sch_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .smbus_xfer = sch_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .functionality = sch_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct i2c_adapter sch_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .algo = &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int smbus_sch_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) res = platform_get_resource(dev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!devm_request_region(&dev->dev, res->start, resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sch_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sch_smba = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* set up the sysfs linkage to our parent device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sch_adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) snprintf(sch_adapter.name, sizeof(sch_adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "SMBus SCH adapter at %04x", sch_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) retval = i2c_add_adapter(&sch_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sch_smba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int smbus_sch_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (sch_smba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) i2c_del_adapter(&sch_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sch_smba = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct platform_driver smbus_sch_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "isch_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .probe = smbus_sch_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .remove = smbus_sch_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) module_platform_driver(smbus_sch_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_DESCRIPTION("Intel SCH SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_ALIAS("platform:isch_smbus");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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