^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <Peter dot Milne at D hyphen TACQ dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef I2C_IOP3XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define I2C_IOP3XX_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * iop321 hardware bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IOP3XX_ICR_FAST_MODE 0x8000 /* 1=400kBps, 0=100kBps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IOP3XX_ICR_UNIT_RESET 0x4000 /* 1=RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IOP3XX_ICR_SAD_IE 0x2000 /* 1=Slave Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IOP3XX_ICR_ALD_IE 0x1000 /* 1=Arb Loss Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IOP3XX_ICR_SSD_IE 0x0800 /* 1=Slave STOP Detect Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IOP3XX_ICR_BERR_IE 0x0400 /* 1=Bus Error Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IOP3XX_ICR_RXFULL_IE 0x0200 /* 1=Receive Full Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IOP3XX_ICR_TXEMPTY_IE 0x0100 /* 1=Transmit Empty Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IOP3XX_ICR_GCD 0x0080 /* 1=General Call Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * when sending a master mode general call message from the I2C unit"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IOP3XX_ICR_UE 0x0040 /* 1=Unit Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * "NOTE: To avoid I2C bus integrity problems,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * the user needs to ensure that the GPIO Output Data Register -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * GPOD bits associated with an I2C port are cleared prior to setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the enable bit for that I2C serial port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The user prepares to enable I2C port 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IOP3XX_ICR_SCLEN 0x0020 /* 1=SCL enable for master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IOP3XX_ICR_MABORT 0x0010 /* 1=Send a STOP with no data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * NB TBYTE must be clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IOP3XX_ICR_TBYTE 0x0008 /* 1=Send/Receive a byte. i2c clears */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IOP3XX_ICR_NACK 0x0004 /* 1=reply with NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IOP3XX_ICR_MSTOP 0x0002 /* 1=send a STOP after next data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IOP3XX_ICR_MSTART 0x0001 /* 1=initiate a START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IOP3XX_ISR_BERRD 0x0400 /* 1=BUS ERROR Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IOP3XX_ISR_SAD 0x0200 /* 1=Slave ADdress Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IOP3XX_ISR_GCAD 0x0100 /* 1=General Call Address Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IOP3XX_ISR_RXFULL 0x0080 /* 1=Receive Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IOP3XX_ISR_TXEMPTY 0x0040 /* 1=Transmit Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IOP3XX_ISR_ALD 0x0020 /* 1=Arbitration Loss Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IOP3XX_ISR_SSD 0x0010 /* 1=Slave STOP Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IOP3XX_ISR_BBUSY 0x0008 /* 1=Bus BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IOP3XX_ISR_UNITBUSY 0x0004 /* 1=Unit Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IOP3XX_ISR_NACK 0x0002 /* 1=Unit Rx or Tx a NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IOP3XX_ISR_RXREAD 0x0001 /* 1=READ 0=WRITE (R/W bit of slave addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IOP3XX_ISR_CLEARBITS 0x07f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IOP3XX_ISAR_SAMASK 0x007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IOP3XX_IDBR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IOP3XX_IBMR_SCL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IOP3XX_IBMR_SDA 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IOP3XX_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IOP3XX_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MYSAR 0 /* default slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_ERR 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_ERR_BERR (I2C_ERR+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_ERR_ALD (I2C_ERR+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CR_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SR_OFFSET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SAR_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DBR_OFFSET 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCR_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BMR_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IOP3XX_I2C_IO_SIZE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_algo_iop3xx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 SR_enabled, SR_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct gpio_desc *gpio_scl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct gpio_desc *gpio_sda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif /* I2C_IOP3XX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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