^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* ------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <Peter dot Milne at D hyphen TACQ dot com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With acknowledgements to i2c-algo-ibm_ocp.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * - Make it work with IXP46x chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - Cleanup function names, coding style, etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * - writing to slave address causes latchup on iop331.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * fix: driver refuses to address self.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "i2c-iop3xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* global unit counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int i2c_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline unsigned char
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) iic_cook_addr(struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned char addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) addr = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Follows devman 9.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Every time unit enable is asserted, GPOD needs to be cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * on IOP3XX to avoid data corruption on the bus. We use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * gpiod_set_raw_value() to make sure the 0 hits the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * GPOD register. These descriptors are only passed along to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the device if this is necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (iop3xx_adap->gpio_scl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) gpiod_set_raw_value(iop3xx_adap->gpio_scl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (iop3xx_adap->gpio_sda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) gpiod_set_raw_value(iop3xx_adap->gpio_sda, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* NB SR bits not same position as CR IE bits :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iop3xx_adap->SR_enabled =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * NB: the handler has to clear the source of the interrupt!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Then it passes the SR flags of interest to BH via adap data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if ((sr &= iop3xx_adap->SR_enabled)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) iop3xx_adap->SR_received |= sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) wake_up_interruptible(&iop3xx_adap->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* check all error conditions, clear them , report most important */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iop3xx_i2c_error(u32 sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if ((sr & IOP3XX_ISR_BERRD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if ( !rc ) rc = -I2C_ERR_BERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((sr & IOP3XX_ISR_ALD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if ( !rc ) rc = -I2C_ERR_ALD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_lock_irqsave(&iop3xx_adap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) sr = iop3xx_adap->SR_received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) iop3xx_adap->SR_received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * sleep until interrupted, then recover and analyse the SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * saved by handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) typedef int (* compare_func)(unsigned test, unsigned mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* returns 1 on correct comparison */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned flags, unsigned* status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) compare_func compare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned sr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int interrupted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) interrupted = wait_event_interruptible_timeout (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) iop3xx_adap->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 1 * HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if ((rc = iop3xx_i2c_error(sr)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *status = sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else if (!interrupted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *status = sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } while(!done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *status = sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Concrete compare_funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) all_bits_clear(unsigned test, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return (test & mask) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) any_bits_set(unsigned test, unsigned mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return (test & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return iop3xx_i2c_wait_event(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iop3xx_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) status, any_bits_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return iop3xx_i2c_wait_event(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) iop3xx_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) status, any_bits_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return iop3xx_i2c_wait_event(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct i2c_msg* msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* avoid writing to my slave address (hangs on 80331),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * forbidden in Intel developer manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (msg->addr == MYSAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cr &= ~IOP3XX_ICR_MSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cr |= IOP3XX_ICR_MSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cr &= ~IOP3XX_ICR_MSTOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cr |= IOP3XX_ICR_TBYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cr &= ~IOP3XX_ICR_MSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cr |= IOP3XX_ICR_TBYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (ii = 0; rc == 0 && ii != count; ++ii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (ii = 0; rc == 0 && ii != count; ++ii)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Description: This function implements combined transactions. Combined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * transactions consist of combinations of reading and writing blocks of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * FROM THE SAME ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Each transfer (i.e. a read or a write) is separated by a repeated start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if ((pmsg->flags&I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * master_xfer() - main read/write entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int im = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) iop3xx_i2c_wait_idle(iop3xx_adap, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) iop3xx_i2c_reset(iop3xx_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) iop3xx_i2c_enable(iop3xx_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (im = 0; ret == 0 && im != num; im++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) iop3xx_i2c_transaction_cleanup(iop3xx_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if(ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return im;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) iop3xx_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct i2c_algorithm iop3xx_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .master_xfer = iop3xx_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .functionality = iop3xx_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) iop3xx_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct i2c_adapter *padapter = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i2c_algo_iop3xx_data *adapter_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (struct i2c_algo_iop3xx_data *)padapter->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Disable the actual HW unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) iounmap(adapter_data->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) kfree(adapter_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) kfree(padapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) iop3xx_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct i2c_adapter *new_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct i2c_algo_iop3xx_data *adapter_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!new_adapter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!adapter_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) goto free_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) adapter_data->gpio_scl = devm_gpiod_get_optional(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (IS_ERR(adapter_data->gpio_scl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = PTR_ERR(adapter_data->gpio_scl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto free_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) adapter_data->gpio_sda = devm_gpiod_get_optional(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (IS_ERR(adapter_data->gpio_sda)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = PTR_ERR(adapter_data->gpio_sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto free_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto free_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto free_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* set the adapter enumeration # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) adapter_data->id = i2c_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!adapter_data->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pdev->name, adapter_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) new_adapter->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) new_adapter->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) new_adapter->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) new_adapter->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Default values...should these come in from board code?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) new_adapter->timeout = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) new_adapter->algo = &iop3xx_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) init_waitqueue_head(&adapter_data->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_lock_init(&adapter_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) iop3xx_i2c_reset(adapter_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) iop3xx_i2c_enable(adapter_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) platform_set_drvdata(pdev, new_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) new_adapter->algo_data = adapter_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) i2c_add_numbered_adapter(new_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) iounmap(adapter_data->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) free_both:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) kfree(adapter_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) free_adapter:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) kfree(new_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct of_device_id i2c_iop3xx_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { .compatible = "intel,iop3xx-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { .compatible = "intel,ixp4xx-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_DEVICE_TABLE(of, i2c_iop3xx_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct platform_driver iop3xx_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .probe = iop3xx_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .remove = iop3xx_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "IOP3xx-I2C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .of_match_table = i2c_iop3xx_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) module_platform_driver(iop3xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MODULE_ALIAS("platform:IOP3xx-I2C");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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