^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 Motorola GSG-China
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Darius Augulis, Teltonika Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Desc.:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Implementation of I2C Adapter/Algorithm Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for I2C Bus integrated in Freescale i.MX/MXC processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Derived from Motorola GSG China I2C example driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2007 RightHand Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/i2c-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* This will be the driver name the kernel reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRIVER_NAME "imx-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Enable DMA if transfer byte size is bigger than this threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * As the hardware request, it must bigger than 4 bytes.\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * I have set '16' here, maybe it's not the best but I think it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * the appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA_THRESHOLD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* IMX I2C registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * the I2C register offset is different between SoCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * to provid support for all these chips, split the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * register offset into a fixed base address and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * variable shift value, then the full register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * will be calculated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * reg_off = ( reg_base_addr << reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX_I2C_IADR 0x00 /* i2c slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX_I2C_I2CR 0x02 /* i2c control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX_I2C_I2SR 0x03 /* i2c status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX_I2C_REGSHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define VF610_I2C_REGSHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Bits of IMX I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2SR_RXAK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2SR_IIF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2SR_SRW 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2SR_IAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2SR_IBB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2SR_IAAS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2SR_ICF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2CR_DMAEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2CR_RSTA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2CR_TXAK 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2CR_MTX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2CR_MSTA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2CR_IIEN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2CR_IEN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* register bits different operating codes definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * 1) I2SR: Interrupt flags clear operation differ between SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * - write zero to clear(w0c) INT flag on i.MX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * - but write one to clear(w1c) INT flag on Vybrid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 2) I2CR: I2C module enable operation also differ between SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * - set I2CR_IEN bit enable the module on i.MX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * - but clear I2CR_IEN bit enable the module on Vybrid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2SR_CLR_OPCODE_W0C 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define I2CR_IEN_OPCODE_0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I2CR_IEN_OPCODE_1 I2CR_IEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define I2C_PM_TIMEOUT 10 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * sorted list of clock divider, register value pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * taken from table 26-5, p.26-9, Freescale i.MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Integrated Portable System Processor Reference Manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Duplicated divider values removed from list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct imx_i2c_clk_pair {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 3072, 0x1E }, { 3840, 0x1F }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Vybrid VF610 clock divider, register value pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum imx_i2c_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IMX1_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) IMX21_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) VF610_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct imx_i2c_hwdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum imx_i2c_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct imx_i2c_clk_pair *clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned ndivs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned i2sr_clr_opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned i2cr_ien_opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct imx_i2c_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dma_chan *chan_using;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dma_addr_t dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum dma_transfer_direction dma_transfer_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) enum dma_data_direction dma_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct imx_i2c_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct notifier_block clk_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) wait_queue_head_t queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long i2csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int disable_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int ifdr; /* IMX_I2C_IFDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int cur_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const struct imx_i2c_hwdata *hwdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct i2c_bus_recovery_info rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct pinctrl_state *pinctrl_pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct pinctrl_state *pinctrl_pins_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct imx_i2c_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .devtype = IMX1_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .regshift = IMX_I2C_REGSHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .clk_div = imx_i2c_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .devtype = IMX21_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .regshift = IMX_I2C_REGSHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .clk_div = imx_i2c_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct imx_i2c_hwdata vf610_i2c_hwdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .devtype = VF610_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .regshift = VF610_I2C_REGSHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .clk_div = vf610_i2c_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct platform_device_id imx_i2c_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "imx21-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct of_device_id i2c_imx_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct acpi_device_id i2c_imx_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return i2c_imx->hwdata->devtype == IMX1_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline void imx_i2c_write_reg(unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct imx_i2c_struct *i2c_imx, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Functions for DMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dma_addr_t phy_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct imx_i2c_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct dma_slave_config dma_sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct device *dev = &i2c_imx->adapter.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma->chan_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(dma->chan_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ret = PTR_ERR(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret != -ENODEV && ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) goto fail_al;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dma_sconfig.dst_addr = phy_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dma_sconfig.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dma_sconfig.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(dev, "can't configure tx channel (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto fail_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dma->chan_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (IS_ERR(dma->chan_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = PTR_ERR(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret != -ENODEV && ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto fail_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_sconfig.src_addr = phy_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dma_sconfig.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dma_sconfig.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(dev, "can't configure rx channel (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) goto fail_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) i2c_imx->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) init_completion(&dma->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fail_rx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dma_release_channel(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) fail_tx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) fail_al:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) devm_kfree(dev, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void i2c_imx_dma_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct imx_i2c_dma *dma = i2c_imx->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dma->dma_len, dma->dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) complete(&dma->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct i2c_msg *msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct imx_i2c_dma *dma = i2c_imx->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct dma_async_tx_descriptor *txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct device *dev = &i2c_imx->adapter.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct device *chan_dev = dma->chan_using->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dma->dma_len, dma->dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (dma_mapping_error(chan_dev, dma->dma_buf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(dev, "DMA mapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto err_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma->dma_len, dma->dma_transfer_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!txdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "Not able to get desc for DMA xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto err_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) reinit_completion(&dma->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) txdesc->callback = i2c_imx_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) txdesc->callback_param = i2c_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (dma_submit_error(dmaengine_submit(txdesc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(dev, "DMA submit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto err_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dma_async_issue_pending(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) err_submit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) err_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dma_unmap_single(chan_dev, dma->dma_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dma->dma_len, dma->dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) err_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct imx_i2c_dma *dma = i2c_imx->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dma->dma_buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dma->dma_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dma_release_channel(dma->chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dma->chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dma_release_channel(dma->chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dma->chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dma->chan_using = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* check for arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (temp & I2SR_IAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (for_busy && (temp & I2SR_IBB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i2c_imx->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!for_busy && !(temp & I2SR_IBB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) i2c_imx->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "<%s> I2C bus is busy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (atomic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * The formula for the poll timeout is documented in the RM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Rev.5 on page 1878:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * T_min = 10/F_scl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Set the value hard as it is done for the non-atomic use-case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Use 10 kHz for the calculation since this is the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * allowed SMBus frequency. Also add an offset of 100us since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * turned out that the I2SR_IIF bit isn't set correctly within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * the minimum timeout in polling mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i2c_imx->i2csr = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* check for arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (i2c_imx->i2csr & I2SR_IAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) i2c_imx->i2csr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) i2c_imx->i2csr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENXIO; /* No ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int i2c_clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Divider value calculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (i2c_imx->cur_clk == i2c_clk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) i2c_imx->cur_clk = i2c_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (div < i2c_clk_div[0].div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) i = i2c_imx->hwdata->ndivs - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (i = 0; i2c_clk_div[i].div < div; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Store divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) i2c_imx->ifdr = i2c_clk_div[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * There dummy delay is calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * It should be about one I2C clock period long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * This delay is used in I2C bus disable function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * to fix chip hardware bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #ifdef CONFIG_I2C_DEBUG_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) i2c_clk_rate, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i2c_clk_div[i].val, i2c_clk_div[i].div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long action, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct imx_i2c_struct *i2c_imx = container_of(nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct imx_i2c_struct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clk_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (action & POST_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) i2c_imx_set_clk(i2c_imx, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Enable I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Wait controller to be stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) usleep_range(50, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Start I2C transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) temp |= I2CR_MSTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) temp &= ~I2CR_IIEN; /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) temp &= ~I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!i2c_imx->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Stop I2C transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!(temp & I2CR_MSTA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) i2c_imx->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) temp &= ~(I2CR_MSTA | I2CR_MTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (i2c_imx->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) temp &= ~I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (is_imx1_i2c(i2c_imx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * This delay caused by an i.MXL hardware bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * If no (or too short) delay, no "STOP" bit will be generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) udelay(i2c_imx->disable_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!i2c_imx->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) i2c_imx_bus_busy(i2c_imx, 0, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Disable I2C controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct imx_i2c_struct *i2c_imx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (temp & I2SR_IIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* save status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) i2c_imx->i2csr = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) wake_up(&i2c_imx->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct i2c_msg *msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned int temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct imx_i2c_dma *dma = i2c_imx->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct device *dev = &i2c_imx->adapter.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dma->chan_using = dma->chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dma->dma_transfer_dir = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dma->dma_data_dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dma->dma_len = msgs->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) result = i2c_imx_dma_xfer(i2c_imx, msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) temp |= I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Write slave address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * The first byte must be transmitted by the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) time_left = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) &i2c_imx->dma->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msecs_to_jiffies(DMA_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Waiting for transfer complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (temp & I2SR_ICF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (time_after(jiffies, orig_jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) msecs_to_jiffies(DMA_TIMEOUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_dbg(dev, "<%s> Timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) temp &= ~I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* The last data byte must be transferred by the CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) imx_i2c_write_reg(msgs->buf[msgs->len-1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) result = i2c_imx_trx_complete(i2c_imx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return i2c_imx_acked(i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct i2c_msg *msgs, bool is_lastmsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct imx_i2c_dma *dma = i2c_imx->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct device *dev = &i2c_imx->adapter.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma->chan_using = dma->chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dma->dma_transfer_dir = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dma->dma_data_dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* The last two data bytes must be transferred by the CPU. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dma->dma_len = msgs->len - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) result = i2c_imx_dma_xfer(i2c_imx, msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) time_left = wait_for_completion_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) &i2c_imx->dma->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) msecs_to_jiffies(DMA_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* waiting for transfer complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (temp & I2SR_ICF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (time_after(jiffies, orig_jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) msecs_to_jiffies(DMA_TIMEOUT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_dbg(dev, "<%s> Timeout\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) temp &= ~I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* read n-1 byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) temp |= I2CR_TXAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* read n byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) result = i2c_imx_trx_complete(i2c_imx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (is_lastmsg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * It must generate STOP before read I2DR to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * controller from generating another clock cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_dbg(dev, "<%s> clear MSTA\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!(temp & I2CR_MSTA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) i2c_imx->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) temp &= ~(I2CR_MSTA | I2CR_MTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!i2c_imx->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) i2c_imx_bus_busy(i2c_imx, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * For i2c master receiver repeat restart operation like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * read -> repeat MSTA -> read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * The controller must set MTX before read the last byte in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * the first read operation, otherwise the first read cost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * one extra clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) temp |= I2CR_MTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int i, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __func__, i2c_8bit_addr_from_msg(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* write slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) result = i2c_imx_trx_complete(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) result = i2c_imx_acked(i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for (i = 0; i < msgs->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "<%s> write byte: B%d=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) __func__, i, msgs->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) result = i2c_imx_trx_complete(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) result = i2c_imx_acked(i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) bool is_lastmsg, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int i, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int block_data = msgs->flags & I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "<%s> write slave address: addr=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) __func__, i2c_8bit_addr_from_msg(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* write slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) result = i2c_imx_trx_complete(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) result = i2c_imx_acked(i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* setup bus to read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) temp &= ~I2CR_MTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * Reset the I2CR_TXAK flag initially for SMBus block read since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * length is unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if ((msgs->len - 1) || block_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) temp &= ~I2CR_TXAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) temp |= I2CR_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) for (i = 0; i < msgs->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u8 len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) result = i2c_imx_trx_complete(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * First byte is the length of remaining packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * in the SMBus block data read. Add it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * msgs->len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if ((!i) && block_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "<%s> read length: 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __func__, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) msgs->len += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (i == (msgs->len - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (is_lastmsg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * It must generate STOP before read I2DR to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * controller from generating another clock cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "<%s> clear MSTA\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!(temp & I2CR_MSTA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) i2c_imx->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) temp &= ~(I2CR_MSTA | I2CR_MTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!i2c_imx->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) i2c_imx_bus_busy(i2c_imx, 0, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * For i2c master receiver repeat restart operation like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * read -> repeat MSTA -> read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * The controller must set MTX before read the last byte in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * the first read operation, otherwise the first read cost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * one extra clock cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) temp |= I2CR_MTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) } else if (i == (msgs->len - 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "<%s> set TXAK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) temp |= I2CR_TXAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if ((!i) && block_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) msgs->buf[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "<%s> read byte: B%d=0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) __func__, i, msgs->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct i2c_msg *msgs, int num, bool atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) unsigned int i, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) bool is_lastmsg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Start I2C transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) result = i2c_imx_start(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * Bus recovery uses gpiod_get_value_cansleep() which is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * allowed within atomic context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (!atomic && i2c_imx->adapter.bus_recovery_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) i2c_recover_bus(&i2c_imx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) result = i2c_imx_start(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* read/write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (i == num - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) is_lastmsg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "<%s> repeated start\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) temp |= I2CR_RSTA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "<%s> transfer message: %d\n", __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* write/read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #ifdef CONFIG_I2C_DEBUG_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_dbg(&i2c_imx->adapter.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) (temp & I2SR_RXAK ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (msgs[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (!atomic &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* Stop I2C transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) i2c_imx_stop(i2c_imx, atomic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) (result < 0) ? "error" : "success msg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) (result < 0) ? result : num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return (result < 0) ? result : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int i2c_imx_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) result = i2c_imx_xfer_common(adapter, msgs, num, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) result = clk_enable(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) result = i2c_imx_xfer_common(adapter, msgs, num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) clk_disable(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct imx_i2c_struct *i2c_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct imx_i2c_struct *i2c_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * We switch SCL and SDA to their GPIO function and do some bitbanging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * for bus recovery. These alternative pinmux settings can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * described in the device tree by a separate pinctrl state "gpio". If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * this is missing this is not a big problem, the only implication is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * that we can't do bus recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return PTR_ERR(i2c_imx->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) } else if (IS_ERR(rinfo->sda_gpiod) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) IS_ERR(rinfo->scl_gpiod) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) IS_ERR(i2c_imx->pinctrl_pins_default) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_dbg(&pdev->dev, "recovery information incomplete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev_dbg(&pdev->dev, "using scl%s for recovery\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rinfo->sda_gpiod ? ",sda" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) rinfo->prepare_recovery = i2c_imx_prepare_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) rinfo->recover_bus = i2c_generic_scl_recovery;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) i2c_imx->adapter.bus_recovery_info = rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static u32 i2c_imx_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const struct i2c_algorithm i2c_imx_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .master_xfer = i2c_imx_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .master_xfer_atomic = i2c_imx_xfer_atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .functionality = i2c_imx_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int i2c_imx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct imx_i2c_struct *i2c_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dma_addr_t phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) const struct imx_i2c_hwdata *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_dbg(&pdev->dev, "<%s>\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) phy_addr = (dma_addr_t)res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!i2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) match = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) i2c_imx->hwdata = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) i2c_imx->hwdata = (struct imx_i2c_hwdata *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Setup i2c_imx driver structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) i2c_imx->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) i2c_imx->adapter.algo = &i2c_imx_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) i2c_imx->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) i2c_imx->adapter.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) i2c_imx->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* Get I2C clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (IS_ERR(i2c_imx->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "can't get I2C clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = clk_prepare_enable(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* Init queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) init_waitqueue_head(&i2c_imx->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Set up adapter data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Set up platform driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) platform_set_drvdata(pdev, i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto rpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Request IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pdev->name, i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(&pdev->dev, "can't claim irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto rpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Set up clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "clock-frequency", &i2c_imx->bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (ret < 0 && pdata && pdata->bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2c_imx->bitrate = pdata->bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Set up chip registers to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Init optional bus recovery function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Give it another chance if pinctrl used is not ready yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) goto clk_notifier_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* Add I2C adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) goto clk_notifier_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) i2c_imx->adapter.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Init DMA config if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) i2c_imx_dma_request(i2c_imx, phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0; /* Return OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) clk_notifier_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) free_irq(irq, i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) rpm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) clk_disable_unprepare(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int i2c_imx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = pm_runtime_resume_and_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* remove adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) i2c_del_adapter(&i2c_imx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (i2c_imx->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) i2c_imx_dma_free(i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* setup chip registers to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) free_irq(irq, i2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) clk_disable_unprepare(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) clk_disable(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret = clk_enable(i2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const struct dev_pm_ops i2c_imx_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) i2c_imx_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static struct platform_driver i2c_imx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .probe = i2c_imx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .remove = i2c_imx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .pm = &i2c_imx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .of_match_table = i2c_imx_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .acpi_match_table = i2c_imx_acpi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .id_table = imx_i2c_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int __init i2c_adap_imx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return platform_driver_register(&i2c_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) subsys_initcall(i2c_adap_imx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static void __exit i2c_adap_imx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) platform_driver_unregister(&i2c_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) module_exit(i2c_adap_imx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) MODULE_AUTHOR("Darius Augulis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) MODULE_ALIAS("platform:" DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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