^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This is i.MX low power i2c controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_NAME "imx-lpi2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPI2C_PARAM 0x04 /* i2c RX/TX FIFO size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPI2C_MCR 0x10 /* i2c contrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPI2C_MSR 0x14 /* i2c status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPI2C_MIER 0x18 /* i2c interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPI2C_MCFGR0 0x20 /* i2c master configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPI2C_MCFGR1 0x24 /* i2c master configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPI2C_MCFGR2 0x28 /* i2c master configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPI2C_MCFGR3 0x2C /* i2c master configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPI2C_MCCR0 0x48 /* i2c master clk configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPI2C_MCCR1 0x50 /* i2c master clk configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPI2C_MFCR 0x58 /* i2c master FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPI2C_MFSR 0x5C /* i2c master FIFO status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPI2C_MTDR 0x60 /* i2c master TX data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPI2C_MRDR 0x70 /* i2c master RX data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* i2c command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TRAN_DATA 0X00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RECV_DATA 0X01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GEN_STOP 0X02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RECV_DISCARD 0X03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GEN_START 0X04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define START_NACK 0X05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define START_HIGH 0X06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define START_HIGH_NACK 0X07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCR_MEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCR_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCR_DOZEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCR_DBGEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MCR_RTF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MCR_RRF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MSR_TDF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MSR_RDF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MSR_SDF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSR_NDF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MSR_ALF BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MSR_MBF BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MSR_BBF BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MIER_TDIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MIER_RDIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MIER_SDIE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MIER_NDIE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MCFGR1_AUTOSTOP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MCFGR1_IGNACK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MRDR_RXEMPTY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_CLK_RATIO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CHUNK_DATA 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_PM_TIMEOUT 10 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum lpi2c_imx_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) STANDARD, /* 100+Kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FAST, /* 400+Kbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FAST_PLUS, /* 1.0+Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) HS, /* 3.4+Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ULTRA_FAST, /* 5.0+Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum lpi2c_imx_pincfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) TWO_PIN_OD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) TWO_PIN_OO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) TWO_PIN_PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FOUR_PIN_PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct lpi2c_imx_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u8 *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u8 *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int msglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int delivered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int block_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int txfifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int rxfifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum lpi2c_imx_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel(enable, lpi2c_imx->base + LPI2C_MIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int lpi2c_imx_bus_busy(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) temp = readl(lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* check for arbitration lost, clear if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (temp & MSR_ALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(temp, lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (temp & (MSR_BBF | MSR_MBF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_dbg(&lpi2c_imx->adapter.dev, "bus not work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void lpi2c_imx_set_mode(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int bitrate = lpi2c_imx->bitrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum lpi2c_imx_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (bitrate < I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mode = STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else if (bitrate < I2C_MAX_FAST_MODE_PLUS_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mode = FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) else if (bitrate < I2C_MAX_HIGH_SPEED_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mode = FAST_PLUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else if (bitrate < I2C_MAX_ULTRA_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mode = HS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mode = ULTRA_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) lpi2c_imx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int lpi2c_imx_start(struct lpi2c_imx_struct *lpi2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct i2c_msg *msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) temp = readl(lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) temp |= MCR_RRF | MCR_RTF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel(temp, lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) writel(0x7f00, lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) temp = i2c_8bit_addr_from_msg(msgs) | (GEN_START << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(temp, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return lpi2c_imx_bus_busy(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel(GEN_STOP << 8, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) temp = readl(lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (temp & MSR_SDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_dbg(&lpi2c_imx->adapter.dev, "stop timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 prescale, filt, sethold, clkhi, clklo, datavd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int clk_rate, clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) enum lpi2c_imx_pincfg pincfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) lpi2c_imx_set_mode(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clk_rate = clk_get_rate(lpi2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (lpi2c_imx->mode == HS || lpi2c_imx->mode == ULTRA_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) filt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) filt = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for (prescale = 0; prescale <= 7; prescale++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) - 3 - (filt >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) clkhi = (clk_cycle + I2C_CLK_RATIO) / (I2C_CLK_RATIO + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clklo = clk_cycle - clkhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (clklo < 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (prescale > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* set MCFGR1: PINCFG, PRESCALE, IGNACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (lpi2c_imx->mode == ULTRA_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pincfg = TWO_PIN_OO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pincfg = TWO_PIN_OD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) temp = prescale | pincfg << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (lpi2c_imx->mode == ULTRA_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) temp |= MCFGR1_IGNACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writel(temp, lpi2c_imx->base + LPI2C_MCFGR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* set MCFGR2: FILTSDA, FILTSCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) temp = (filt << 16) | (filt << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel(temp, lpi2c_imx->base + LPI2C_MCFGR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* set MCCR: DATAVD, SETHOLD, CLKHI, CLKLO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sethold = clkhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) datavd = clkhi >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) temp = datavd << 24 | sethold << 16 | clkhi << 8 | clklo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (lpi2c_imx->mode == HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel(temp, lpi2c_imx->base + LPI2C_MCCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(temp, lpi2c_imx->base + LPI2C_MCCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) temp = MCR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(temp, lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(0, lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = lpi2c_imx_config(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto rpm_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) temp = readl(lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) temp |= MCR_MEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(temp, lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rpm_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int lpi2c_imx_master_disable(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) temp = readl(lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) temp &= ~MCR_MEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) writel(temp, lpi2c_imx->base + LPI2C_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pm_runtime_mark_last_busy(lpi2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pm_runtime_put_autosuspend(lpi2c_imx->adapter.dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) timeout = wait_for_completion_timeout(&lpi2c_imx->complete, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return timeout ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int lpi2c_imx_txfifo_empty(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long orig_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_dbg(&lpi2c_imx->adapter.dev, "NDF detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(&lpi2c_imx->adapter.dev, "txfifo empty timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } while (txcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void lpi2c_imx_set_tx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(lpi2c_imx->txfifosize >> 1, lpi2c_imx->base + LPI2C_MFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void lpi2c_imx_set_rx_watermark(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int temp, remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (remaining > (lpi2c_imx->rxfifosize >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) temp = lpi2c_imx->rxfifosize >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(temp << 16, lpi2c_imx->base + LPI2C_MFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void lpi2c_imx_write_txfifo(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int data, txcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) txcnt = readl(lpi2c_imx->base + LPI2C_MFSR) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) while (txcnt < lpi2c_imx->txfifosize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (lpi2c_imx->delivered == lpi2c_imx->msglen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data = lpi2c_imx->tx_buf[lpi2c_imx->delivered++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(data, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) txcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (lpi2c_imx->delivered < lpi2c_imx->msglen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) lpi2c_imx_intctrl(lpi2c_imx, MIER_TDIE | MIER_NDIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) complete(&lpi2c_imx->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void lpi2c_imx_read_rxfifo(struct lpi2c_imx_struct *lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int blocklen, remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int temp, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) data = readl(lpi2c_imx->base + LPI2C_MRDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (data & MRDR_RXEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) lpi2c_imx->rx_buf[lpi2c_imx->delivered++] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * First byte is the length of remaining packet in the SMBus block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * data read. Add it to msgs->len.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (lpi2c_imx->block_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) blocklen = lpi2c_imx->rx_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) lpi2c_imx->msglen += blocklen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) remaining = lpi2c_imx->msglen - lpi2c_imx->delivered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) complete(&lpi2c_imx->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* not finished, still waiting for rx data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) lpi2c_imx_set_rx_watermark(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* multiple receive commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (lpi2c_imx->block_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) lpi2c_imx->block_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) temp = remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) temp |= (RECV_DATA << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel(temp, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else if (!(lpi2c_imx->delivered & 0xff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) temp = (remaining > CHUNK_DATA ? CHUNK_DATA : remaining) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) temp |= (RECV_DATA << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel(temp, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void lpi2c_imx_write(struct lpi2c_imx_struct *lpi2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct i2c_msg *msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) lpi2c_imx->tx_buf = msgs->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) lpi2c_imx_set_tx_watermark(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) lpi2c_imx_write_txfifo(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void lpi2c_imx_read(struct lpi2c_imx_struct *lpi2c_imx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct i2c_msg *msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) lpi2c_imx->rx_buf = msgs->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lpi2c_imx->block_data = msgs->flags & I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) lpi2c_imx_set_rx_watermark(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) temp = msgs->len > CHUNK_DATA ? CHUNK_DATA - 1 : msgs->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) temp |= (RECV_DATA << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel(temp, lpi2c_imx->base + LPI2C_MTDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int lpi2c_imx_xfer(struct i2c_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int i, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) result = lpi2c_imx_master_enable(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) result = lpi2c_imx_start(lpi2c_imx, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* quick smbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (num == 1 && msgs[0].len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) lpi2c_imx->delivered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) lpi2c_imx->msglen = msgs[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) init_completion(&lpi2c_imx->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (msgs[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) lpi2c_imx_read(lpi2c_imx, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) lpi2c_imx_write(lpi2c_imx, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) result = lpi2c_imx_msg_complete(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!(msgs[i].flags & I2C_M_RD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) result = lpi2c_imx_txfifo_empty(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) lpi2c_imx_stop(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) temp = readl(lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if ((temp & MSR_NDF) && !result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) lpi2c_imx_master_disable(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_dbg(&lpi2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (result < 0) ? "error" : "success msg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) (result < 0) ? result : num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return (result < 0) ? result : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct lpi2c_imx_struct *lpi2c_imx = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) lpi2c_imx_intctrl(lpi2c_imx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) temp = readl(lpi2c_imx->base + LPI2C_MSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (temp & MSR_RDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) lpi2c_imx_read_rxfifo(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (temp & MSR_TDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) lpi2c_imx_write_txfifo(lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (temp & MSR_NDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) complete(&lpi2c_imx->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static u32 lpi2c_imx_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) I2C_FUNC_SMBUS_READ_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct i2c_algorithm lpi2c_imx_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .master_xfer = lpi2c_imx_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .functionality = lpi2c_imx_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct of_device_id lpi2c_imx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { .compatible = "fsl,imx7ulp-lpi2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int lpi2c_imx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct lpi2c_imx_struct *lpi2c_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) lpi2c_imx = devm_kzalloc(&pdev->dev, sizeof(*lpi2c_imx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!lpi2c_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(lpi2c_imx->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return PTR_ERR(lpi2c_imx->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) lpi2c_imx->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) lpi2c_imx->adapter.algo = &lpi2c_imx_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) lpi2c_imx->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) strlcpy(lpi2c_imx->adapter.name, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sizeof(lpi2c_imx->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) lpi2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (IS_ERR(lpi2c_imx->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev_err(&pdev->dev, "can't get I2C peripheral clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return PTR_ERR(lpi2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "clock-frequency", &lpi2c_imx->bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pdev->name, lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(&pdev->dev, "can't claim irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) i2c_set_adapdata(&lpi2c_imx->adapter, lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) platform_set_drvdata(pdev, lpi2c_imx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = clk_prepare_enable(lpi2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(&pdev->dev, "clk enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) temp = readl(lpi2c_imx->base + LPI2C_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) lpi2c_imx->txfifosize = 1 << (temp & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) lpi2c_imx->rxfifosize = 1 << ((temp >> 8) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = i2c_add_adapter(&lpi2c_imx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto rpm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_info(&lpi2c_imx->adapter.dev, "LPI2C adapter registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rpm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pm_runtime_put(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int lpi2c_imx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct lpi2c_imx_struct *lpi2c_imx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) i2c_del_adapter(&lpi2c_imx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int __maybe_unused lpi2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk_disable_unprepare(lpi2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int __maybe_unused lpi2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = clk_prepare_enable(lpi2c_imx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const struct dev_pm_ops lpi2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) lpi2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct platform_driver lpi2c_imx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .probe = lpi2c_imx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .remove = lpi2c_imx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .of_match_table = lpi2c_imx_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .pm = &lpi2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) module_platform_driver(lpi2c_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_DESCRIPTION("I2C adapter driver for LPI2C bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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