^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/i2c/busses/i2c-ibm_iic.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the IIC peripheral on IBM PPC 4xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003 Zultys Technologies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on original work by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Ian DaSilva <idasilva@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Armin Kuster <akuster@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Matt Porter <mporter@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright 2000-2003 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef __I2C_IBM_IIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define __I2C_IBM_IIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct iic_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u16 mdbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u16 sbbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 lmadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 hmadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 mdcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 extsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 lsadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 hsadr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 intmsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 xfrcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 xtcntlss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 directcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ibm_iic_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) volatile struct iic_regs __iomem *vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int fast_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 clckdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* IICx_CNTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CNTL_HMT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CNTL_AMD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CNTL_TCT_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CNTL_TCT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CNTL_RPST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CNTL_CHT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CNTL_RW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CNTL_PT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* IICx_MDCNTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MDCNTL_FSDB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MDCNTL_FMDB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MDCNTL_EGC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MDCNTL_FSM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MDCNTL_ESM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MDCNTL_EINT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MDCNTL_EUBS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MDCNTL_HSCL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* IICx_STS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STS_SSS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STS_SLPR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STS_MDBS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STS_MDBF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STS_SCMP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STS_ERR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STS_IRQA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STS_PT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* IICx_EXTSTS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EXTSTS_IRQP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EXTSTS_BCS_MASK 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EXTSTS_BCS_FREE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EXTSTS_IRQD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define EXTSTS_LA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EXTSTS_ICT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EXTSTS_XFRA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* IICx_INTRMSK register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define INTRMSK_EIRC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define INTRMSK_EIRS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define INTRMSK_EIWC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define INTRMSK_EIWS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define INTRMSK_EIHE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define INTRMSK_EIIC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INTRMSK_EITA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTRMSK_EIMTC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* IICx_XFRCNT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define XFRCNT_MTC_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* IICx_XTCNTLSS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XTCNTLSS_SRC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XTCNTLSS_SRS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XTCNTLSS_SWC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XTCNTLSS_SWS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XTCNTLSS_SRST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* IICx_DIRECTCNTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DIRCNTL_SDAC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DIRCNTL_SCC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DIRCNTL_MSDA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DIRCNTL_MSC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Check if we really control the I2C bus and bus is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* __I2C_IBM_IIC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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