^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/i2c/busses/i2c-ibm_iic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the IIC peripheral on IBM PPC 4xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2003, 2004 Zultys Technologies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 2008 PIKA Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Sean MacLennan <smaclennan@pikatech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Based on original work by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Ian DaSilva <idasilva@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Armin Kuster <akuster@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Matt Porter <mporter@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright 2000-2003 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Original driver version was highly leveraged from i2c-elektor.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Copyright 1995-97 Simon G. Vogl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 1998-99 Hans Berglund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * and even Frodo Looijaard <frodol@dds.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "i2c-ibm_iic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRIVER_VERSION "2.2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static bool iic_force_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param(iic_force_poll, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static bool iic_force_fast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param(iic_force_fast, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DBG_LEVEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #undef DBG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef DBG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #undef DBG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #if DBG_LEVEL > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define DBG(f,x...) ((void)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #if DBG_LEVEL > 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define DBG2(f,x...) DBG(f, ##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define DBG2(f,x...) ((void)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #if DBG_LEVEL > 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) " cntl = 0x%02x, mdcntl = 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) " sts = 0x%02x, extsts = 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) " clkdiv = 0x%02x, xfrcnt = 0x%02x\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) " xtcntlss = 0x%02x, directcntl = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) in_8(&iic->xtcntlss), in_8(&iic->directcntl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define DUMP_REGS(h,dev) dump_iic_regs((h),(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define DUMP_REGS(h,dev) ((void)0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Bus timings (in ns) for bit-banging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct ibm_iic_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int hd_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int su_sto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } timings [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Standard mode (100 KHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .hd_sta = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .su_sto = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .low = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .high = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .buf = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Fast mode (400 KHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .hd_sta = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .su_sto = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .low = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .high = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .buf = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Enable/disable interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Initialize IIC interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void iic_dev_init(struct ibm_iic_private* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DBG("%d: init\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Clear master address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) out_8(&iic->lmadr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) out_8(&iic->hmadr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Clear slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out_8(&iic->lsadr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) out_8(&iic->hsadr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Clear status & extended status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) out_8(&iic->sts, STS_SCMP | STS_IRQA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) | EXTSTS_ICT | EXTSTS_XFRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Set clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) out_8(&iic->clkdiv, dev->clckdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Clear transfer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) out_8(&iic->xfrcnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Clear extended control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) | XTCNTLSS_SWS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Clear control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) out_8(&iic->cntl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Enable interrupts if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) iic_interrupt_mode(dev, dev->irq >= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Set mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | (dev->fast_mode ? MDCNTL_FSM : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) DUMP_REGS("iic_init", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Reset IIC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void iic_dev_reset(struct ibm_iic_private* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 dc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DBG("%d: soft reset\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DUMP_REGS("reset", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Place chip in the reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out_8(&iic->xtcntlss, XTCNTLSS_SRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Check if bus is free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dc = in_8(&iic->directcntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!DIRCTNL_FREE(dc)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DBG("%d: trying to regain bus control\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Try to set bus free state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Wait until we regain bus control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (i = 0; i < 100; ++i){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dc = in_8(&iic->directcntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (DIRCTNL_FREE(dc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Toggle SCL line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dc ^= DIRCNTL_SCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) out_8(&iic->directcntl, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dc ^= DIRCNTL_SCC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) out_8(&iic->directcntl, dc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* be nice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Remove reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) out_8(&iic->xtcntlss, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Reinitialize interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) iic_dev_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Wait for SCL and/or SDA to be high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long x = jiffies + HZ / 28 + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) while ((in_8(&iic->directcntl) & mask) != mask){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (unlikely(time_after(jiffies, x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 mask, v, sda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int i, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Only 7-bit addresses are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (unlikely(p->flags & I2C_M_TEN)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Reset IIC interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) out_8(&iic->xtcntlss, XTCNTLSS_SRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Wait for bus to become free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ndelay(t->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) out_8(&iic->directcntl, DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sda = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ndelay(t->hd_sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Send address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) v = i2c_8bit_addr_from_msg(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) out_8(&iic->directcntl, sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ndelay(t->low / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sda = (v & mask) ? DIRCNTL_SDAC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) out_8(&iic->directcntl, sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ndelay(t->low / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) out_8(&iic->directcntl, DIRCNTL_SCC | sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ndelay(t->high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) out_8(&iic->directcntl, sda);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ndelay(t->low / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) out_8(&iic->directcntl, DIRCNTL_SDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ndelay(t->low / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ndelay(t->high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) out_8(&iic->directcntl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ndelay(t->low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) out_8(&iic->directcntl, DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ndelay(t->su_sto);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ndelay(t->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Remove reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) out_8(&iic->xtcntlss, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Reinitialize interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) iic_dev_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) res = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * IIC interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static irqreturn_t iic_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Acknowledge IRQ and wakeup iic_wait_for_tc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) out_8(&iic->sts, STS_IRQA | STS_SCMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) wake_up_interruptible(&dev->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Get master transfer result and clear errors if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Returns the number of actually transferred bytes or error (<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int iic_xfer_result(struct ibm_iic_private* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (unlikely(in_8(&iic->sts) & STS_ERR)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) in_8(&iic->extsts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Clear errors and possible pending IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Flush master data buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Is bus free?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * If error happened during combined xfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * IIC interface is usually stuck in some strange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * state, the only way out - soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DBG("%d: bus is stuck, resetting\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) iic_dev_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * Try to abort active transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void iic_abort_xfer(struct ibm_iic_private* dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DBG("%d: iic_abort_xfer\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) out_8(&iic->cntl, CNTL_HMT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Wait for the abort command to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * It's not worth to be optimized, just poll (timeout >= 1 tick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) x = jiffies + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (time_after(jiffies, x)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DBG("%d: abort timeout, resetting...\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) iic_dev_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Just to clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) iic_xfer_result(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Wait for master transfer to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * It puts current process to sleep until we get interrupt or timeout expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Returns the number of transferred bytes or error (<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int iic_wait_for_tc(struct ibm_iic_private* dev){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (dev->irq >= 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = wait_event_interruptible_timeout(dev->wq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DBG("%d: wait interrupted\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else if (unlikely(in_8(&iic->sts) & STS_PT)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DBG("%d: wait timeout\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned long x = jiffies + dev->adap.timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) while (in_8(&iic->sts) & STS_PT){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (unlikely(time_after(jiffies, x))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DBG("%d: poll timeout\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (signal_pending(current)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DBG("%d: poll interrupted\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = -ERESTARTSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) iic_abort_xfer(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = iic_xfer_result(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Low level master transfer routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int combined_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) char* buf = pm->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int i, j, loops, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int len = pm->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (pm->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cntl |= CNTL_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) loops = (len + 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) for (i = 0; i < loops; ++i, len -= 4){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int count = len > 4 ? 4 : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!(cntl & CNTL_RW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (j = 0; j < count; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) out_8((void __iomem *)&iic->mdbuf, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (i < loops - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cmd |= CNTL_CHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) else if (combined_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cmd |= CNTL_RPST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Start transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) out_8(&iic->cntl, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = iic_wait_for_tc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if (unlikely(ret != count)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DBG("%d: xfer_bytes, requested %d, transferred %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev->idx, count, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* If it's not a last part of xfer, abort it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (combined_xfer || (i < loops - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) iic_abort_xfer(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (cntl & CNTL_RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (j = 0; j < count; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *buf++ = in_8((void __iomem *)&iic->mdbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret > 0 ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Set target slave address for master transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u16 addr = msg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) addr, msg->flags & I2C_M_TEN ? 10 : 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (msg->flags & I2C_M_TEN){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) out_8(&iic->cntl, CNTL_AMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out_8(&iic->lmadr, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) out_8(&iic->cntl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) out_8(&iic->lmadr, addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static inline int iic_invalid_address(const struct i2c_msg* p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static inline int iic_address_neq(const struct i2c_msg* p1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct i2c_msg* p2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return (p1->addr != p2->addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * Generic master transfer entrypoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * Returns the number of processed messages or error (<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) volatile struct iic_regs __iomem *iic = dev->vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Check the sanity of the passed messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Uhh, generic i2c layer is more suitable place for such code...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (unlikely(iic_invalid_address(&msgs[0]))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (i = 0; i < num; ++i){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (unlikely(msgs[i].len <= 0)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (num == 1 && !msgs[0].len){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Special case for I2C_SMBUS_QUICK emulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * IBM IIC doesn't support 0-length transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * so we have to emulate them using bit-banging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return iic_smbus_quick(dev, &msgs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msgs[i].len, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Check bus state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DBG("%d: iic_xfer, bus is not free\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Usually it means something serious has happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * We *cannot* have unfinished previous transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * so it doesn't make any sense to try to stop it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Probably we were not able to recover from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * previous error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * The only *reasonable* thing I can think of here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * is soft reset. --ebs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) iic_dev_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Flush master data buffer (just in case) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Load slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) iic_address(dev, &msgs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Do real transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0; i < num && !ret; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret < 0 ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static u32 iic_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct i2c_algorithm iic_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .master_xfer = iic_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .functionality = iic_func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static inline u8 iic_clckdiv(unsigned int opb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Compatibility kludge, should go away after all cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * are fixed to fill correct value for opbfreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * Previous driver version used hardcoded divider value 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * it corresponds to OPB frequency from the range (40, 50] MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!opb){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) " fix your board specific setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) opb = 50000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Convert to MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) opb /= 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (opb < 20 || opb > 150){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) opb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) opb = opb < 20 ? 20 : 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return (u8)((opb + 9) / 10 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int iic_request_irq(struct platform_device *ofdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct ibm_iic_private *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (iic_force_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Disable interrupts until we finish initialization, assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * level-sensitive IRQ setup...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) iic_interrupt_mode(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Fallback to the polling mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * Register single IIC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static int iic_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct ibm_iic_private *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const u32 *freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(&ofdev->dev, "failed to allocate device data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) platform_set_drvdata(ofdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev->vaddr = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (dev->vaddr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(&ofdev->dev, "failed to iomap device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) goto error_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) init_waitqueue_head(&dev->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev->irq = iic_request_irq(ofdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_warn(&ofdev->dev, "using polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Board specific settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev->fast_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) freq = of_get_property(np, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (freq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) freq = of_get_property(np->parent, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (freq == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_err(&ofdev->dev, "Unable to get bus frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) goto error_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev->clckdiv = iic_clckdiv(*freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Initialize IIC interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) iic_dev_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Register it with i2c layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) adap = &dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) adap->dev.parent = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) adap->dev.of_node = of_node_get(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) adap->algo = &iic_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) adap->timeout = HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto error_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_info(&ofdev->dev, "using %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) error_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) iic_interrupt_mode(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (dev->vaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) iounmap(dev->vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Cleanup initialized IIC interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int iic_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) i2c_del_adapter(&dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) iic_interrupt_mode(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) iounmap(dev->vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const struct of_device_id ibm_iic_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) { .compatible = "ibm,iic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) MODULE_DEVICE_TABLE(of, ibm_iic_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct platform_driver ibm_iic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .name = "ibm-iic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .of_match_table = ibm_iic_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .probe = iic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .remove = iic_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) module_platform_driver(ibm_iic_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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