^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) <mdsxyz123@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Copyright (C) 2010 Intel Corporation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) David Woodhouse <dwmw2@infradead.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Supports the following Intel I/O Controller Hubs (ICH):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * I/O Block I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * region SMBus Block proc. block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Chip name PCI ID size PEC buffer call read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 82801AA (ICH) 0x2413 16 no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 82801AB (ICH0) 0x2423 16 no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 82801BA (ICH2) 0x2443 16 no no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 82801CA (ICH3) 0x2483 32 soft no no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 82801DB (ICH4) 0x24c3 32 hard yes no no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 82801E (ICH5) 0x24d3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 6300ESB 0x25a4 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 82801F (ICH6) 0x266a 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 82801G (ICH7) 0x27da 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 82801H (ICH8) 0x283e 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 82801I (ICH9) 0x2930 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ICH10 0x3a30 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * ICH10 0x3a60 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * 6 Series (PCH) 0x1c22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Patsburg (PCH) 0x1d22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Panther Point (PCH) 0x1e22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Avoton (SOC) 0x1f3c 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * BayTrail (SOC) 0x0f12 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Braswell (SOC) 0x2292 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * DNV (SOC) 0x19df 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Broxton (SOC) 0x5ad4 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Features supported by this driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Software PEC no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Hardware PEC yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Block buffer yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Block process call transaction yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * I2C block read transaction yes (doesn't use the block buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Slave mode no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * SMBus Host Notify yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Interrupt processing yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * See the file Documentation/i2c/busses/i2c-i801.rst for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #include <linux/i2c-smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <linux/platform_data/itco_wdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #include <linux/platform_data/i2c-mux-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* I801 SMBus address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SMBHSTSTS(p) (0 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SMBHSTCNT(p) (2 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SMBHSTCMD(p) (3 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SMBHSTADD(p) (4 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SMBHSTDAT0(p) (5 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SMBHSTDAT1(p) (6 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SMBBLKDAT(p) (7 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* PCI Address Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SMBBAR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SMBPCICTL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SMBPCISTS 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SMBHSTCFG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TCOBASE 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TCOCTL 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SBREG_BAR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SBREG_SMBCTRL 0xc6000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SBREG_SMBCTRL_DNV 0xcf000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Host status bits for SMBPCISTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SMBPCISTS_INTS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Control bits for SMBPCICTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SMBPCICTL_INTDIS BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Host configuration bits for SMBHSTCFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SMBHSTCFG_HST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SMBHSTCFG_SMB_SMI_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SMBHSTCFG_I2C_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SMBHSTCFG_SPD_WD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* TCO configuration bits for TCOCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TCOCTL_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Auxiliary status register bits, ICH4+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SMBAUXSTS_CRCE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SMBAUXSTS_STCO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Auxiliary control register bits, ICH4+ only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SMBAUXCTL_CRC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SMBAUXCTL_E32B BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MAX_RETRIES 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* I801 command constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define I801_QUICK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define I801_BYTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define I801_BYTE_DATA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define I801_WORD_DATA 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define I801_PROC_CALL 0x10 /* unimplemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define I801_BLOCK_DATA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define I801_BLOCK_PROC_CALL 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* I801 Host Control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SMBHSTCNT_INTREN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SMBHSTCNT_KILL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SMBHSTCNT_LAST_BYTE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SMBHSTCNT_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* I801 Hosts Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SMBHSTSTS_BYTE_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SMBHSTSTS_INUSE_STS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SMBHSTSTS_SMBALERT_STS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SMBHSTSTS_FAILED BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SMBHSTSTS_BUS_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SMBHSTSTS_DEV_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SMBHSTSTS_INTR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SMBHSTSTS_HOST_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Host Notify Status register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SMBSLVSTS_HST_NTFY_STS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Host Notify Command register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SMBHSTSTS_DEV_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) STATUS_ERROR_FLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Older devices have their ID defined in <linux/pci_ids.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct i801_mux_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) char *gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned values[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int n_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned classes[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned gpios[2]; /* Relative to gpio_chip->base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int n_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct i801_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long smba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char original_hstcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned char original_slvcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* isr processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Command state used by isr for byte-by-byte block transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bool is_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) const struct i801_mux_config *mux_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct platform_device *mux_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct gpiod_lookup_table *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct platform_device *tco_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * If set to true the host controller registers are reserved for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * ACPI AML use. Protected by acpi_lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bool acpi_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct mutex acpi_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define FEATURE_SMBUS_PEC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define FEATURE_BLOCK_BUFFER BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define FEATURE_BLOCK_PROC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define FEATURE_I2C_BLOCK_READ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define FEATURE_IRQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define FEATURE_HOST_NOTIFY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Not really a feature, but it's convenient to handle it as such */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define FEATURE_IDF BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define FEATURE_TCO_SPT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define FEATURE_TCO_CNL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const char *i801_feature_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "SMBus PEC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Block buffer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Block process call",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "I2C block read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Interrupt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "SMBus Host Notify",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static unsigned int disable_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) module_param(disable_features, uint, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "\t\t 0x01 disable SMBus PEC\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "\t\t 0x02 disable the block buffer\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "\t\t 0x08 disable the I2C block read functionality\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "\t\t 0x10 don't use interrupts\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "\t\t 0x20 disable SMBus Host Notify ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Make sure the SMBus host is ready to start transmitting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) Return 0 if it is, -EBUSY if it is not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int i801_check_pre(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) status = inb_p(SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (status & SMBHSTSTS_HOST_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) status &= STATUS_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) outb_p(status, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Failed clearing status flags (%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Clear CRC status if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * During normal operation, i801_check_post() takes care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * of it after every operation. We do it here only in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * the hardware was already in this state when the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (priv->features & FEATURE_SMBUS_PEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_dbg(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "Clearing aux status flags (%02x)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) outb_p(status, SMBAUXSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Failed clearing aux status flags (%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Convert the status register to an error code, and clear it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Note that status only contains the bits we want to clear, not the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * actual register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int i801_check_post(struct i801_priv *priv, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * If the SMBus is still busy, we give up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Note: This timeout condition only happens when using polling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * transactions. For interrupt operation, NAK/timeout is indicated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * DEV_ERR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (unlikely(status < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* try to stop the current command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) outb_p(0, SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Check if it worked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) status = inb_p(SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if ((status & SMBHSTSTS_HOST_BUSY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) !(status & SMBHSTSTS_FAILED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "Failed terminating the transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (status & SMBHSTSTS_FAILED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(&priv->pci_dev->dev, "Transaction failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (status & SMBHSTSTS_DEV_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * This may be a PEC error, check and clear it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * AUXSTS is handled differently from HSTSTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * For HSTSTS, i801_isr() or i801_wait_intr()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * has already cleared the error bits in hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * and we are passed a copy of the original value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * in "status".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * For AUXSTS, the hardware register is left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * for us to handle here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * This is asymmetric, slightly iffy, but safe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * since all this code is serialized and the CRCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * bit is harmless as long as it's cleared before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * the next operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if ((priv->features & FEATURE_SMBUS_PEC) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) result = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_dbg(&priv->pci_dev->dev, "PEC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_dbg(&priv->pci_dev->dev, "No response\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (status & SMBHSTSTS_BUS_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) result = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Clear status flags except BYTE_DONE, to be cleared by caller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) outb_p(status, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Wait for BUSY being cleared and either INTR or an error flag being set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int i801_wait_intr(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* We will always wait for a fraction of a second! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) usleep_range(250, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) status = inb_p(SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } while (((status & SMBHSTSTS_HOST_BUSY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) (timeout++ < MAX_RETRIES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (timeout > MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Wait for either BYTE_DONE or an error flag being set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int i801_wait_byte_done(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* We will always wait for a fraction of a second! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) usleep_range(250, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) status = inb_p(SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (timeout++ < MAX_RETRIES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (timeout > MAX_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return status & STATUS_ERROR_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int i801_transaction(struct i801_priv *priv, int xact)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const struct i2c_adapter *adap = &priv->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) result = i801_check_pre(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (priv->features & FEATURE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) result = wait_event_timeout(priv->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (status = priv->status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_warn(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Timeout waiting for interrupt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) priv->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return i801_check_post(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* the current contents of SMBHSTCNT can be overwritten, since PEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * SMBSCMD are passed in xact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) status = i801_wait_intr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return i801_check_post(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int i801_block_transaction_by_block(struct i801_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) union i2c_smbus_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) char read_write, int command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int hwpec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) switch (command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) xact |= I801_BLOCK_PROC_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) xact |= I801_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Use 32-byte buffer to process this transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) outb_p(len, SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) outb_p(data->block[i+1], SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) status = i801_transaction(priv, xact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (read_write == I2C_SMBUS_READ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) command == I2C_SMBUS_BLOCK_PROC_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) len = inb_p(SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) data->block[i + 1] = inb_p(SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void i801_isr_byte_done(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (priv->is_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* For SMBus block reads, length is received with first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) (priv->count == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) priv->len = inb_p(SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "Illegal SMBus block read size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) priv->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* FIXME: Recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) priv->len = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_dbg(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "SMBus block read size is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) priv->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) priv->data[-1] = priv->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Read next byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (priv->count < priv->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) priv->data[priv->count++] = inb(SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "Discarding extra byte on block read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Set LAST_BYTE for last byte of read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (priv->count == priv->len - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else if (priv->count < priv->len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Write next byte, except for IRQ after last byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Clear BYTE_DONE to continue with next byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned short addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) addr = inb_p(SMBNTFDADD(priv)) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * always returns 0. Our current implementation doesn't provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * data, so we just ignore it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) i2c_handle_smbus_host_notify(&priv->adapter, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* clear Host Notify bit and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * There are three kinds of interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * 1) i801 signals transaction completion with one of these interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * INTR - Success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * DEV_ERR - Invalid command, NAK or communication timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * BUS_ERR - SMI# transaction collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * FAILED - transaction was canceled due to a KILL request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * When any of these occur, update ->status and wake up the waitq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * ->status must be cleared before kicking off the next transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * occurs for each byte of a byte-by-byte to prepare the next byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * 3) Host Notify interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static irqreturn_t i801_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct i801_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u16 pcists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Confirm this is our interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!(pcists & SMBPCISTS_INTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (priv->features & FEATURE_HOST_NOTIFY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) status = inb_p(SMBSLVSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (status & SMBSLVSTS_HST_NTFY_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return i801_host_notify_isr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) status = inb_p(SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (status & SMBHSTSTS_BYTE_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) i801_isr_byte_done(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * Clear irq sources and report transaction result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * ->status must be cleared before the next transaction is started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) outb_p(status, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) priv->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) wake_up(&priv->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * For "byte-by-byte" block transactions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * I2C read uses cmd=I801_I2C_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) union i2c_smbus_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) char read_write, int command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int hwpec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int smbcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const struct i2c_adapter *adap = &priv->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (command == I2C_SMBUS_BLOCK_PROC_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) result = i801_check_pre(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (result < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) outb_p(len, SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) outb_p(data->block[1], SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) smbcmd = I801_I2C_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) smbcmd = I801_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (priv->features & FEATURE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) priv->is_read = (read_write == I2C_SMBUS_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (len == 1 && priv->is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) smbcmd |= SMBHSTCNT_LAST_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) priv->cmd = smbcmd | SMBHSTCNT_INTREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) priv->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) priv->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) priv->data = &data->block[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) result = wait_event_timeout(priv->waitq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (status = priv->status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) status = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_warn(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "Timeout waiting for interrupt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) priv->status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return i801_check_post(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) for (i = 1; i <= len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (i == len && read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) smbcmd |= SMBHSTCNT_LAST_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) outb_p(smbcmd, SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SMBHSTCNT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) status = i801_wait_byte_done(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (i == 1 && read_write == I2C_SMBUS_READ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) && command != I2C_SMBUS_I2C_BLOCK_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) len = inb_p(SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "Illegal SMBus block read size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Recover */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) while (inb_p(SMBHSTSTS(priv)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SMBHSTSTS_HOST_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) outb_p(SMBHSTSTS_BYTE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Retrieve/store value in SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) data->block[i] = inb_p(SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) outb_p(data->block[i+1], SMBBLKDAT(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* signals SMBBLKDAT ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) status = i801_wait_intr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return i801_check_post(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int i801_set_block_buffer_mode(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Block transaction function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int i801_block_transaction(struct i801_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) union i2c_smbus_data *data, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int command, int hwpec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned char hostc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) data->block[0] = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* set I2C_EN bit in configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hostc | SMBHSTCFG_I2C_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_err(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "I2C block read is unsupported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Experience has shown that the block buffer can only be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) SMBus (not I2C) block transactions, even though the datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) doesn't mention this limitation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((priv->features & FEATURE_BLOCK_BUFFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) && command != I2C_SMBUS_I2C_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) && i801_set_block_buffer_mode(priv) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) result = i801_block_transaction_by_block(priv, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) command, hwpec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) result = i801_block_transaction_byte_by_byte(priv, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) command, hwpec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (command == I2C_SMBUS_I2C_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) && read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* restore saved configuration register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static s32 i801_access(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned short flags, char read_write, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int hwpec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ret = 0, xact = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct i801_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mutex_lock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (priv->acpi_reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) mutex_unlock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pm_runtime_get_sync(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) && size != I2C_SMBUS_QUICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) && size != I2C_SMBUS_I2C_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) xact = I801_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) xact = I801_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) outb_p(data->byte, SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) xact = I801_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) outb_p(data->word & 0xff, SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) xact = I801_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * NB: page 240 of ICH5 datasheet shows that the R/#W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * bit should be cleared here, even when reading.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * However if SPD Write Disable is set (Lynx Point and later),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) * the read will fail if we don't set the R/#W bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) outb_p(((addr & 0x7f) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) (read_write & 0x01) : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* NB: page 240 of ICH5 datasheet also shows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * that DATA1 is the cmd field when reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) outb_p(command, SMBHSTDAT1(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * Bit 0 of the slave address register always indicate a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) outb_p(command, SMBHSTCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) block = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (hwpec) /* enable/disable hardware PEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SMBAUXCTL(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = i801_block_transaction(priv, data, read_write, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hwpec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = i801_transaction(priv, xact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* Some BIOSes don't like it when PEC is enabled at reboot or resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) time, so we forcibly disable it after every transaction. Turn off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) E32B for the same reason. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (hwpec || block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) outb_p(inb_p(SMBAUXCTL(priv)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) switch (xact & 0x7f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case I801_BYTE: /* Result put in SMBHSTDAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case I801_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) data->byte = inb_p(SMBHSTDAT0(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) case I801_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) data->word = inb_p(SMBHSTDAT0(priv)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (inb_p(SMBHSTDAT1(priv)) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Unlock the SMBus device for use by BIOS/ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pm_runtime_mark_last_busy(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pm_runtime_put_autosuspend(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) mutex_unlock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static u32 i801_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct i801_priv *priv = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ((priv->features & FEATURE_BLOCK_PROC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ((priv->features & FEATURE_I2C_BLOCK_READ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ((priv->features & FEATURE_HOST_NOTIFY) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static void i801_enable_host_notify(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct i801_priv *priv = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!(priv->features & FEATURE_HOST_NOTIFY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) SMBSLVCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* clear Host Notify bit to allow a new notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static void i801_disable_host_notify(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (!(priv->features & FEATURE_HOST_NOTIFY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .smbus_xfer = i801_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .functionality = i801_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const struct pci_device_id i801_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) MODULE_DEVICE_TABLE(pci, i801_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #if defined CONFIG_X86 && defined CONFIG_DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static unsigned char apanel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Scan the system ROM for the signature "FJKEYINF" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static __init const void __iomem *bios_signature(const void __iomem *bios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ssize_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) const unsigned char signature[] = "FJKEYINF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) for (offset = 0; offset < 0x10000; offset += 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (check_signature(bios + offset, signature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) sizeof(signature)-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return bios + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static void __init input_apanel_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) void __iomem *bios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) const void __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) bios = ioremap(0xF0000, 0x10000); /* Can't fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) p = bios_signature(bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* just use the first address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) apanel_addr = readb(p + 8 + 3) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) iounmap(bios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct dmi_onboard_device_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned short i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) const char *i2c_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const struct dmi_onboard_device_info dmi_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static void dmi_check_onboard_device(u8 type, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct i2c_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* & ~0x80, ignore enabled/disabled bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if ((type & ~0x80) != dmi_devices[i].type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (strcasecmp(name, dmi_devices[i].name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) info.addr = dmi_devices[i].i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) i2c_new_client_device(adap, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* We use our own function to check for onboard devices instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dmi_find_device() as some buggy BIOS's have the devices we are interested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) in marked as disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (dm->type != 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) count = (dm->length - sizeof(struct dmi_header)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) const u8 *d = (char *)(dm + 1) + (i * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) const char *name = ((char *) dm) + dm->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u8 type = d[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u8 s = d[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) s--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) while (s > 0 && name[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) name += strlen(name) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) s--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (name[0] == 0) /* Bogus string reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dmi_check_onboard_device(type, name, adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const char *const acpi_smo8800_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) "SMO8800",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "SMO8801",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "SMO8810",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "SMO8811",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "SMO8820",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "SMO8821",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "SMO8830",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) "SMO8831",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u32 nesting_level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) void **return_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct acpi_device_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) char *hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) status = acpi_get_object_info(obj_handle, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!(info->valid & ACPI_VALID_HID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) goto smo88xx_not_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) hid = info->hardware_id.string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!hid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) goto smo88xx_not_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto smo88xx_not_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) *((bool *)return_value) = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return AE_CTRL_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) smo88xx_not_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static bool is_dell_system_with_lis3lv02d(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) bool found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) const char *vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) vendor = dmi_get_system_info(DMI_SYS_VENDOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!vendor || strcmp(vendor, "Dell Inc."))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * Check that ACPI device SMO88xx is present and is functioning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * Function acpi_get_devices() already filters all ACPI devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * which are not present or are not functioning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * accelerometer but unfortunately ACPI does not provide any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * information (like I2C address).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) (void **)&found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * Accelerometer's I2C address is not specified in DMI nor ACPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * so it is needed to define mapping table based on DMI product names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) const char *dmi_product_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) unsigned short i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) } dell_lis3lv02d_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * Dell platform team told us that these Latitude devices have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * ST microelectronics accelerometer at I2C address 0x29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) { "Latitude E5250", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) { "Latitude E5450", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) { "Latitude E5550", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) { "Latitude E6440", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { "Latitude E6440 ATG", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) { "Latitude E6540", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * Additional individual entries were added after verification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) { "Latitude 5480", 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) { "Vostro V131", 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct i2c_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) const char *dmi_product_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (strcmp(dmi_product_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dell_lis3lv02d_devices[i].dmi_product_name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dev_warn(&priv->pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "Accelerometer lis3lv02d is present on SMBus but its"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) " address is unknown, skipping registration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) info.addr = dell_lis3lv02d_devices[i].i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) i2c_new_client_device(&priv->adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Register optional slaves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static void i801_probe_optional_slaves(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Only register slaves on main SMBus channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (priv->features & FEATURE_IDF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (apanel_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct i2c_board_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) memset(&info, 0, sizeof(struct i2c_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) info.addr = apanel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) i2c_new_client_device(&priv->adapter, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (dmi_name_in_vendors("FUJITSU"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dmi_walk(dmi_check_onboard_devices, &priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (is_dell_system_with_lis3lv02d())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) register_dell_lis3lv02d_i2c_device(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!priv->mux_drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) i2c_register_spd(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void __init input_apanel_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static void i801_probe_optional_slaves(struct i801_priv *priv) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #endif /* CONFIG_X86 && CONFIG_DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .gpio_chip = "gpio_ich",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .values = { 0x02, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .n_values = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .gpios = { 52, 53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .n_gpios = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .gpio_chip = "gpio_ich",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .values = { 0x02, 0x03, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .n_values = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .gpios = { 52, 53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .n_gpios = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const struct dmi_system_id mux_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .driver_data = &i801_mux_config_asus_z8_d18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .driver_data = &i801_mux_config_asus_z8_d18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .driver_data = &i801_mux_config_asus_z8_d12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* Setup multiplexing if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static int i801_add_mux(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct device *dev = &priv->adapter.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) const struct i801_mux_config *mux_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct i2c_mux_gpio_platform_data gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct gpiod_lookup_table *lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (!priv->mux_drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) mux_config = priv->mux_drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* Prepare the platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) gpio_data.parent = priv->adapter.nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) gpio_data.values = mux_config->values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) gpio_data.n_values = mux_config->n_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) gpio_data.classes = mux_config->classes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* Register GPIO descriptor lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) lookup = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct_size(lookup, table, mux_config->n_gpios + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (!lookup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) lookup->dev_id = "i2c-mux-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) for (i = 0; i < mux_config->n_gpios; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) lookup->table[i] = (struct gpiod_lookup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) GPIO_LOOKUP(mux_config->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) mux_config->gpios[i], "mux", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) gpiod_add_lookup_table(lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) priv->lookup = lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * Register the mux device, we use PLATFORM_DEVID_NONE here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * because since we are referring to the GPIO chip by name we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * anyways in deep trouble if there is more than one of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * devices, and there should likely only be one platform controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * hub.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PLATFORM_DEVID_NONE, &gpio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) sizeof(struct i2c_mux_gpio_platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (IS_ERR(priv->mux_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) err = PTR_ERR(priv->mux_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) gpiod_remove_lookup_table(lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) priv->mux_pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) dev_err(dev, "Failed to register i2c-mux-gpio device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static void i801_del_mux(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (priv->mux_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) platform_device_unregister(priv->mux_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (priv->lookup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) gpiod_remove_lookup_table(priv->lookup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static unsigned int i801_get_adapter_class(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) const struct dmi_system_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) const struct i801_mux_config *mux_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) id = dmi_first_match(mux_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Remove branch classes from trunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) mux_config = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) for (i = 0; i < mux_config->n_values; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) class &= ~mux_config->classes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Remember for later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) priv->mux_drvdata = mux_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static inline void i801_del_mux(struct i801_priv *priv) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return I2C_CLASS_HWMON | I2C_CLASS_SPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static const struct itco_wdt_platform_data spt_tco_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .name = "Intel PCH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .version = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static DEFINE_SPINLOCK(p2sb_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) static struct platform_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct resource *tco_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) unsigned int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) u64 base64_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) u32 base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) u8 hidden;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * We must access the NO_REBOOT bit over the Primary to Sideband
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * bridge (P2SB). The BIOS prevents the P2SB device from being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * enumerated by the PCI subsystem, so we need to unhide/hide it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) * to lookup the P2SB BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) spin_lock(&p2sb_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* Unhide the P2SB device, if it is hidden */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (hidden)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) base64_addr = base_addr & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) base64_addr |= (u64)base_addr << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* Hide the P2SB device, if it was hidden before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (hidden)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) spin_unlock(&p2sb_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) res = &tco_res[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) res->end = res->start + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) tco_res, 2, &spt_tco_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) sizeof(spt_tco_platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const struct itco_wdt_platform_data cnl_tco_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .name = "Intel PCH",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .version = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static struct platform_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct resource *tco_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return platform_device_register_resndata(&pci_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) sizeof(cnl_tco_platform_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static void i801_add_tco(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct pci_dev *pci_dev = priv->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct resource tco_res[2], *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) u32 tco_base, tco_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) /* If we have ACPI based watchdog use that instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (acpi_has_watchdog())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (!(tco_ctl & TCOCTL_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) memset(tco_res, 0, sizeof(tco_res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * Always populate the main iTCO IO resource here. The second entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * for NO_REBOOT MMIO is filled by the SPT specific function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) res = &tco_res[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) res->start = tco_base & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) res->end = res->start + 32 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) res->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (priv->features & FEATURE_TCO_CNL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (IS_ERR(priv->tco_pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) acpi_physical_address address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return address >= priv->smba &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) address <= pci_resource_end(priv->pci_dev, SMBBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static acpi_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) u64 *value, void *handler_context, void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct i801_priv *priv = handler_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct pci_dev *pdev = priv->pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * Once BIOS AML code touches the OpRegion we warn and inhibit any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * further access from the driver itself. This device is now owned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * by the system firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) mutex_lock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) priv->acpi_reserved = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * BIOS is accessing the host controller so prevent it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * suspending automatically from now on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if ((function & ACPI_IO_MASK) == ACPI_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) status = acpi_os_read_port(address, (u32 *)value, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) status = acpi_os_write_port(address, (u32)*value, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) mutex_unlock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int i801_acpi_probe(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) adev = ACPI_COMPANION(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (adev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) status = acpi_install_address_space_handler(adev->handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) NULL, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (ACPI_SUCCESS(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static void i801_acpi_remove(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) adev = ACPI_COMPANION(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) acpi_remove_address_space_handler(adev->handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) mutex_lock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (priv->acpi_reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) pm_runtime_put(&priv->pci_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) mutex_unlock(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static inline void i801_acpi_remove(struct i801_priv *priv) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static unsigned char i801_setup_hstcfg(struct i801_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) unsigned char hstcfg = priv->original_hstcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) hstcfg |= SMBHSTCFG_HST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return hstcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) unsigned char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct i801_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) i2c_set_adapdata(&priv->adapter, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) priv->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) priv->adapter.class = i801_get_adapter_class(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) priv->adapter.algo = &smbus_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) priv->adapter.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) priv->adapter.retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) mutex_init(&priv->acpi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) priv->pci_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) priv->features |= FEATURE_BLOCK_PROC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) priv->features |= FEATURE_I2C_BLOCK_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) priv->features |= FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) priv->features |= FEATURE_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) priv->features |= FEATURE_BLOCK_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) priv->features |= FEATURE_TCO_SPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) priv->features |= FEATURE_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) priv->features |= FEATURE_BLOCK_PROC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) priv->features |= FEATURE_I2C_BLOCK_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) priv->features |= FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) priv->features |= FEATURE_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) priv->features |= FEATURE_BLOCK_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) priv->features |= FEATURE_TCO_CNL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) priv->features |= FEATURE_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) priv->features |= FEATURE_IDF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) priv->features |= FEATURE_BLOCK_PROC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) priv->features |= FEATURE_I2C_BLOCK_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) priv->features |= FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) case PCI_DEVICE_ID_INTEL_82801DB_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) priv->features |= FEATURE_SMBUS_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) priv->features |= FEATURE_BLOCK_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) case PCI_DEVICE_ID_INTEL_82801CA_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) priv->features |= FEATURE_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) case PCI_DEVICE_ID_INTEL_82801BA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) case PCI_DEVICE_ID_INTEL_82801AB_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) case PCI_DEVICE_ID_INTEL_82801AA_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* Disable features on user request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (priv->features & disable_features & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) dev_notice(&dev->dev, "%s disabled by user\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) i801_feature_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) priv->features &= ~disable_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) err = pcim_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pcim_pin_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* Determine the address of the SMBus area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) priv->smba = pci_resource_start(dev, SMBBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (!priv->smba) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) "SMBus base address uninitialized, upgrade BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (i801_acpi_probe(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) err = pcim_iomap_regions(dev, 1 << SMBBAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) dev_driver_string(&dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) "Failed to request SMBus region 0x%lx-0x%Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) priv->smba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) (unsigned long long)pci_resource_end(dev, SMBBAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) i801_acpi_remove(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) temp = i801_setup_hstcfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) dev_info(&dev->dev, "Enabling SMBus device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (temp & SMBHSTCFG_SMB_SMI_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* Disable SMBus interrupt feature if SMBus using SMI# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) priv->features &= ~FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (temp & SMBHSTCFG_SPD_WD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dev_info(&dev->dev, "SPD Write Disable is set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* Clear special mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) outb_p(inb_p(SMBAUXCTL(priv)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* Remember original Host Notify setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (priv->features & FEATURE_HOST_NOTIFY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* Default timeout in interrupt mode: 200 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) priv->adapter.timeout = HZ / 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (dev->irq == IRQ_NOTCONNECTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) priv->features &= ~FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (priv->features & FEATURE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) u16 pcictl, pcists;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* Complain if an interrupt is already pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (pcists & SMBPCISTS_INTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_warn(&dev->dev, "An interrupt is pending!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) /* Check if interrupts have been disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (pcictl & SMBPCICTL_INTDIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) dev_info(&dev->dev, "Interrupts are disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) priv->features &= ~FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (priv->features & FEATURE_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) init_waitqueue_head(&priv->waitq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) dev_driver_string(&dev->dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dev->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) priv->features &= ~FEATURE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev_info(&dev->dev, "SMBus using %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) i801_add_tco(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) snprintf(priv->adapter.name, sizeof(priv->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) "SMBus I801 adapter at %04lx", priv->smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) err = i2c_add_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) i801_acpi_remove(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) i801_enable_host_notify(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) i801_probe_optional_slaves(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* We ignore errors - multiplexing is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) i801_add_mux(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) pci_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) pm_runtime_use_autosuspend(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) pm_runtime_put_autosuspend(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) pm_runtime_allow(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static void i801_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct i801_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) pm_runtime_forbid(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) pm_runtime_get_noresume(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) i801_disable_host_notify(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) i801_del_mux(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) i2c_del_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) i801_acpi_remove(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) platform_device_unregister(priv->tco_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * do not call pci_disable_device(dev) since it can cause hard hangs on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static void i801_shutdown(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct i801_priv *priv = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* Restore config registers to avoid hard hang on some systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) i801_disable_host_notify(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static int i801_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) struct i801_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static int i801_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct i801_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) i801_setup_hstcfg(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) i801_enable_host_notify(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) static struct pci_driver i801_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = "i801_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .id_table = i801_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .probe = i801_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .remove = i801_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .shutdown = i801_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .pm = &i801_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static int __init i2c_i801_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (dmi_name_in_vendors("FUJITSU"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) input_apanel_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return pci_register_driver(&i801_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static void __exit i2c_i801_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) pci_unregister_driver(&i801_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) MODULE_DESCRIPTION("I801 SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) module_init(i2c_i801_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) module_exit(i2c_i801_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags