^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) i2c Support for the Apple `Hydra' Mac I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (c) 1999-2004 Geert Uytterhoeven <geert@linux-m68k.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Based on i2c Support for Via Technologies 82C586B South Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Copyright (c) 1998, 1999 Kyösti Mälkki <kmalkki@cc.hut.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c-algo-bit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/hydra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HYDRA_CPD_PD0 0x00000001 /* CachePD lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HYDRA_CPD_PD1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HYDRA_CPD_PD2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HYDRA_CPD_PD3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HYDRA_SCLK HYDRA_CPD_PD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HYDRA_SDAT HYDRA_CPD_PD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HYDRA_SCLK_OE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HYDRA_SDAT_OE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline void pdregw(void *data, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct Hydra *hydra = (struct Hydra *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) writel(val, &hydra->CachePD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline u32 pdregr(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct Hydra *hydra = (struct Hydra *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return readl(&hydra->CachePD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void hydra_bit_setscl(void *data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 val = pdregr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) val &= ~HYDRA_SCLK_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) val &= ~HYDRA_SCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val |= HYDRA_SCLK_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pdregw(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void hydra_bit_setsda(void *data, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 val = pdregr(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val &= ~HYDRA_SDAT_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val &= ~HYDRA_SDAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val |= HYDRA_SDAT_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pdregw(data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int hydra_bit_getscl(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return (pdregr(data) & HYDRA_SCLK) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int hydra_bit_getsda(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return (pdregr(data) & HYDRA_SDAT) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* ------------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct i2c_algo_bit_data hydra_bit_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .setsda = hydra_bit_setsda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .setscl = hydra_bit_setscl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .getsda = hydra_bit_getsda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .getscl = hydra_bit_getscl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .udelay = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .timeout = HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct i2c_adapter hydra_adap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "Hydra i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .algo_data = &hydra_bit_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct pci_device_id hydra_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_HYDRA) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_DEVICE_TABLE (pci, hydra_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int hydra_probe(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long base = pci_resource_start(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!request_mem_region(base+offsetof(struct Hydra, CachePD), 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hydra_adap.name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) hydra_bit_data.data = pci_ioremap_bar(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (hydra_bit_data.data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) release_mem_region(base+offsetof(struct Hydra, CachePD), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pdregw(hydra_bit_data.data, 0); /* clear SCLK_OE and SDAT_OE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hydra_adap.dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) res = i2c_bit_add_bus(&hydra_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iounmap(hydra_bit_data.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) release_mem_region(base+offsetof(struct Hydra, CachePD), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void hydra_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pdregw(hydra_bit_data.data, 0); /* clear SCLK_OE and SDAT_OE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) i2c_del_adapter(&hydra_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) iounmap(hydra_bit_data.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) release_mem_region(pci_resource_start(dev, 0)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offsetof(struct Hydra, CachePD), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct pci_driver hydra_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "hydra_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .id_table = hydra_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .probe = hydra_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .remove = hydra_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) module_pci_driver(hydra_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DESCRIPTION("i2c for Apple Hydra Mac I/O");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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