^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Now only support 7 bit address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HIX5I2C_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HIX5I2C_COM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HIX5I2C_ICR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HIX5I2C_SR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HIX5I2C_SCL_H 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HIX5I2C_SCL_L 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HIX5I2C_TXR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HIX5I2C_RXR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* I2C_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_UNMASK_TOTAL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_UNMASK_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_UNMASK_END BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_UNMASK_SEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_UNMASK_RECEIVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_UNMASK_ACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_UNMASK_ARBITRATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_UNMASK_OVER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_UNMASK_ALL (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* I2C_COM_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_NO_ACK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_START BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_READ BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_WRITE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* I2C_ICR_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_CLEAR_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_CLEAR_END BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_CLEAR_SEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_CLEAR_RECEIVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_CLEAR_ACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_CLEAR_ARBITRATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_CLEAR_OVER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) I2C_CLEAR_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* I2C_SR_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_START_INTR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_END_INTR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_SEND_INTR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_RECEIVE_INTR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2C_ACK_INTR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2C_ARBITRATE_INTR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_OVER_INTR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum hix5hd2_i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) HIX5I2C_STAT_RW_ERR = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) HIX5I2C_STAT_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) HIX5I2C_STAT_RW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) HIX5I2C_STAT_SND_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) HIX5I2C_STAT_RW_SUCCESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct hix5hd2_i2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spinlock_t lock; /* IRQ synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum hix5hd2_i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(val, priv->regs + HIX5I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) priv->regs + HIX5I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 rate, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 scl, sysclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* close all i2c interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rate = priv->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sysclock = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) scl = (sysclock / (rate * 2)) / 2 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* restore original interrupt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __func__, sysclock, rate, scl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hix5hd2_i2c_disable_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) hix5hd2_i2c_drv_setrate(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) hix5hd2_i2c_clr_all_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hix5hd2_i2c_enable_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hix5hd2_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long stop_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* wait for 100 milli seconds for the bus to be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) stop_time = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int_status = hix5hd2_i2c_clr_pend_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!(int_status & I2C_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) usleep_range(50, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } while (time_before(jiffies, stop_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (priv->state == HIX5I2C_STAT_SND_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->state = HIX5I2C_STAT_RW_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (priv->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv->state = HIX5I2C_STAT_SND_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) hix5hd2_rw_over(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (priv->msg_len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* the last byte don't need send ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else if (priv->msg_len > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* if i2c master receive data will send ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) hix5hd2_rw_handle_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (priv->msg_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) data = priv->msg->buf[priv->msg_idx++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel_relaxed(data, priv->regs + HIX5I2C_TXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) hix5hd2_rw_handle_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (priv->state == HIX5I2C_STAT_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->state = HIX5I2C_STAT_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else if (priv->state == HIX5I2C_STAT_RW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (priv->msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) data = readl_relaxed(priv->regs + HIX5I2C_RXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) priv->msg->buf[priv->msg_idx++] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) priv->msg_len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __func__, priv->state, priv->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct hix5hd2_i2c_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int_status = hix5hd2_i2c_clr_pend_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* handle error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (int_status & I2C_ARBITRATE_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_dbg(priv->dev, "ARB bus loss\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) priv->err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) priv->state = HIX5I2C_STAT_RW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else if (int_status & I2C_ACK_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* ack error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_dbg(priv->dev, "No ACK from device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) priv->err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) priv->state = HIX5I2C_STAT_RW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (int_status & I2C_OVER_INTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (priv->msg_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = hix5hd2_rw_preprocess(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) priv->err = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) priv->state = HIX5I2C_STAT_RW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (priv->msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hix5hd2_read_handle(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hix5hd2_write_handle(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) hix5hd2_rw_over(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) priv->msg->len == priv->msg_idx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (priv->state == HIX5I2C_STAT_RW_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hix5hd2_i2c_disable_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) hix5hd2_i2c_clr_pend_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) complete(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) hix5hd2_i2c_clr_all_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) hix5hd2_i2c_enable_irq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv->regs + HIX5I2C_TXR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct i2c_msg *msgs, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) priv->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) priv->msg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) priv->msg_len = priv->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) priv->stop = stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) priv->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) priv->state = HIX5I2C_STAT_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) reinit_completion(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hix5hd2_i2c_message_start(priv, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) timeout = wait_for_completion_timeout(&priv->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) priv->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) priv->state = HIX5I2C_STAT_RW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) priv->err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_warn(priv->dev, "%s timeout=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) msgs->flags & I2C_M_RD ? "rx" : "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) priv->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = priv->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * If this is the last message to be transfered (stop == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Then check if the bus can be brought back to idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = hix5hd2_i2c_wait_bus_idle(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) hix5hd2_i2c_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return priv->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int i, ret, stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < num; i++, msgs++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) stop = (i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .master_xfer = hix5hd2_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .functionality = hix5hd2_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int hix5hd2_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct hix5hd2_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (of_property_read_u32(np, "clock-frequency", &freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* use 100k as default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) priv->freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (freq > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) priv->freq = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_warn(priv->dev, "use max freq %d instead\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) I2C_MAX_FAST_MODE_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) priv->freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) priv->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (IS_ERR(priv->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return PTR_ERR(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) priv->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) strlcpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) priv->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) priv->adap.algo = &hix5hd2_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) priv->adap.retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) priv->adap.dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) priv->adap.algo_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) priv->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) init_completion(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) hix5hd2_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) IRQF_NO_SUSPEND, dev_name(&pdev->dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pm_runtime_use_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pm_runtime_set_active(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pm_runtime_enable(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = i2c_add_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto err_runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) err_runtime:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pm_runtime_disable(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pm_runtime_set_suspended(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int hix5hd2_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pm_runtime_disable(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pm_runtime_set_suspended(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int hix5hd2_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int hix5hd2_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) hix5hd2_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hix5hd2_i2c_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct of_device_id hix5hd2_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .compatible = "hisilicon,hix5hd2-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static struct platform_driver hix5hd2_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .probe = hix5hd2_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .remove = hix5hd2_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "hix5hd2-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .pm = &hix5hd2_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .of_match_table = hix5hd2_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) module_platform_driver(hix5hd2_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_ALIAS("platform:hix5hd2-i2c");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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