^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas Solutions Highlander FPGA I2C/SMBus support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Supported devices: R0P7780LC0011RL, R0P7785LC0011RL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2008 Atom Create Engineering Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SMCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SMCR_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SMCR_IRIC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SMCR_BBSY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMCR_ACKE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMCR_RST (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SMCR_IEIC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMSMADR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMMR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMMR_MODE0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMMR_MODE1 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMMR_CAP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMMR_TMMD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMMR_SP (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SMSADR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SMTRDR 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct highlander_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long last_read_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) size_t buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static bool iic_force_poll, iic_force_normal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int iic_timeout = 1000, iic_read_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline void highlander_i2c_irq_enable(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline void highlander_i2c_irq_disable(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void highlander_i2c_start(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline void highlander_i2c_done(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void highlander_i2c_setup(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 smmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) smmr = ioread16(dev->base + SMMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) smmr |= SMMR_TMMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (iic_force_normal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) smmr &= ~SMMR_SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) smmr |= SMMR_SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) iowrite16(smmr, dev->base + SMMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void smbus_write_data(u8 *src, u16 *dst, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (; len > 1; len -= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *dst++ = be16_to_cpup((__be16 *)src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) src += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *dst = *src << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void smbus_read_data(u16 *src, u8 *dst, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (; len > 1; len -= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *(__be16 *)dst = cpu_to_be16p(src++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dst += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *dst = *src >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void highlander_i2c_command(struct highlander_i2c_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 command, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 cmd = (command << 8) | command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) for (i = 0; i < len; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (len - i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cmd = command << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) iowrite16(cmd, dev->base + SMSADR + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_dbg(dev->dev, "command data[%x] 0x%04x\n", i/2, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int highlander_i2c_wait_for_bbsy(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) timeout = jiffies + msecs_to_jiffies(iic_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) while (ioread16(dev->base + SMCR) & SMCR_BBSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_warn(dev->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int highlander_i2c_reset(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) iowrite16(ioread16(dev->base + SMCR) | SMCR_RST, dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return highlander_i2c_wait_for_bbsy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int highlander_i2c_wait_for_ack(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 tmp = ioread16(dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if ((tmp & (SMCR_IRIC | SMCR_ACKE)) == SMCR_ACKE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_warn(dev->dev, "ack abnormality\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return highlander_i2c_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static irqreturn_t highlander_i2c_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct highlander_i2c_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) highlander_i2c_done(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void highlander_i2c_poll(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 smcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) timeout = jiffies + msecs_to_jiffies(iic_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) smcr = ioread16(dev->base + SMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Don't bother checking ACKE here, this and the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * are handled in highlander_i2c_wait_xfer_done() when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * waiting for the ACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (smcr & SMCR_IRIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(dev->dev, "polling timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline int highlander_i2c_wait_xfer_done(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) wait_for_completion_timeout(&dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) msecs_to_jiffies(iic_timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* busy looping, the IRQ of champions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) highlander_i2c_poll(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return highlander_i2c_wait_for_ack(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int highlander_i2c_read(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int i, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u16 data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (highlander_i2c_wait_for_bbsy(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) highlander_i2c_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (highlander_i2c_wait_xfer_done(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dev->dev, "Arbitration loss\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * The R0P7780LC0011RL FPGA needs a significant delay between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * data read cycles, otherwise the transceiver gets confused and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * garbage is returned when the read is subsequently aborted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * It is not sufficient to wait for BBSY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * While this generally only applies to the older SH7780-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Highlanders, the same issue can be observed on SH7785 ones,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * albeit less frequently. SH7780-based Highlanders may need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * this to be as high as 1000 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (iic_read_delay && time_before(jiffies, dev->last_read_time +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) msecs_to_jiffies(iic_read_delay)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) msleep(jiffies_to_msecs((dev->last_read_time +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) msecs_to_jiffies(iic_read_delay)) - jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cnt = (dev->buf_len + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) for (i = 0; i < cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) data[i] = ioread16(dev->base + SMTRDR + (i * sizeof(u16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(dev->dev, "read data[%x] 0x%04x\n", i, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) smbus_read_data(data, dev->buf, dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev->last_read_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int highlander_i2c_write(struct highlander_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int i, cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) smbus_write_data(dev->buf, data, dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cnt = (dev->buf_len + 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) iowrite16(data[i], dev->base + SMTRDR + (i * sizeof(u16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_dbg(dev->dev, "write data[%x] 0x%04x\n", i, data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (highlander_i2c_wait_for_bbsy(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) highlander_i2c_start(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return highlander_i2c_wait_xfer_done(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct highlander_i2c_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_dbg(dev->dev, "addr %04x, command %02x, read_write %d, size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) addr, command, read_write, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Set up the buffer and transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev->buf = &data->byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev->buf_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev->buf = &data->block[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev->buf_len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(dev->dev, "unsupported command %d\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Encode the mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) tmp = ioread16(dev->base + SMMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) tmp &= ~(SMMR_MODE0 | SMMR_MODE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (dev->buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tmp |= SMMR_MODE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tmp |= SMMR_MODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tmp |= (SMMR_MODE0 | SMMR_MODE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_err(dev->dev, "unsupported xfer size %zu\n", dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) iowrite16(tmp, dev->base + SMMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Ensure we're in a sane state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) highlander_i2c_done(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) iowrite16((addr << 1) | read_write, dev->base + SMSMADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) highlander_i2c_command(dev, command, dev->buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return highlander_i2c_read(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return highlander_i2c_write(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static u32 highlander_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct i2c_algorithm highlander_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .smbus_xfer = highlander_i2c_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .functionality = highlander_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int highlander_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct highlander_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (unlikely(!res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(&pdev->dev, "no mem resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev = kzalloc(sizeof(struct highlander_i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (unlikely(!dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev->base = ioremap(res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (unlikely(!dev->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (dev->irq < 0 || iic_force_poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = request_irq(dev->irq, highlander_i2c_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pdev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (unlikely(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto err_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) highlander_i2c_irq_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_notice(&pdev->dev, "no IRQ, using polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) highlander_i2c_irq_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev->last_read_time = jiffies; /* initial read jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) highlander_i2c_setup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) adap->class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) adap->algo = &highlander_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) adap->nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Reset the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = highlander_i2c_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(&pdev->dev, "controller didn't come up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&pdev->dev, "failure adding adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) iounmap(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int highlander_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct highlander_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) iounmap(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct platform_driver highlander_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "i2c-highlander",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .probe = highlander_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .remove = highlander_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) module_platform_driver(highlander_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_AUTHOR("Paul Mundt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DESCRIPTION("Renesas Highlander FPGA I2C/SMBus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) module_param(iic_force_poll, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) module_param(iic_force_normal, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) module_param(iic_timeout, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) module_param(iic_read_delay, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_PARM_DESC(iic_force_normal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "Force normal mode (100 kHz), default is fast mode (400 kHz)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_PARM_DESC(iic_timeout, "Set timeout value in msecs (default 1000 ms)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_PARM_DESC(iic_read_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "Delay between data read cycles (default 0 ms)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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