^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FSI-attached I2C master algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * as published by the Free Software Foundation; either version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSI_ENGID_I2C 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_DEFAULT_CLK_DIV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* i2c registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_FSI_FIFO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_FSI_CMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_FSI_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_FSI_WATER_MARK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_FSI_INT_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_FSI_INT_COND 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_FSI_OR_INT_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_FSI_INTS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_FSI_AND_INT_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_FSI_STAT 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_FSI_RESET_I2C 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_FSI_ESTAT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_FSI_RESET_ERR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_FSI_RESID_LEN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_FSI_SET_SCL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_FSI_PORT_BUSY 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_FSI_RESET_SCL 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_FSI_SET_SDA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_FSI_RESET_SDA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* cmd register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_CMD_WITH_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_CMD_WITH_ADDR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_CMD_RD_CONT BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_CMD_WITH_STOP BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_CMD_FORCELAUNCH BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_CMD_ADDR GENMASK(23, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_CMD_READ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_CMD_LEN GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_MODE_CLKDIV GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_MODE_PORT GENMASK(15, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_MODE_ENHANCED BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2C_MODE_DIAG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2C_MODE_PACE_ALLOW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_MODE_WRAP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* watermark register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define I2C_WATERMARK_HI GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2C_WATERMARK_LO GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_FIFO_HI_LVL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_FIFO_LO_LVL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2C_INT_INV_CMD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2C_INT_PARITY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2C_INT_BE_OVERRUN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C_INT_BE_ACCESS BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C_INT_LOST_ARB BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2C_INT_NACK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2C_INT_DAT_REQ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2C_INT_CMD_COMP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2C_INT_STOP_ERR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2C_INT_BUSY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2C_INT_IDLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2C_STAT_INV_CMD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2C_STAT_PARITY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2C_STAT_BE_OVERRUN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2C_STAT_BE_ACCESS BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2C_STAT_LOST_ARB BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2C_STAT_NACK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2C_STAT_DAT_REQ BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define I2C_STAT_CMD_COMP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2C_STAT_STOP_ERR BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I2C_STAT_MAX_PORT GENMASK(22, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define I2C_STAT_ANY_INT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2C_STAT_SCL_IN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define I2C_STAT_SDA_IN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define I2C_STAT_PORT_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I2C_STAT_SELF_BUSY BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I2C_STAT_FIFO_COUNT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define I2C_STAT_ERR (I2C_STAT_INV_CMD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) I2C_STAT_PARITY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) I2C_STAT_BE_OVERRUN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) I2C_STAT_BE_ACCESS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) I2C_STAT_LOST_ARB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) I2C_STAT_NACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) I2C_STAT_STOP_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I2C_STAT_ANY_RESP (I2C_STAT_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) I2C_STAT_DAT_REQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) I2C_STAT_CMD_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* extended status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define I2C_ESTAT_FIFO_SZ GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I2C_ESTAT_SCL_IN_SY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I2C_ESTAT_SDA_IN_SY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define I2C_ESTAT_S_SCL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define I2C_ESTAT_S_SDA BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define I2C_ESTAT_M_SCL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define I2C_ESTAT_M_SDA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define I2C_ESTAT_HI_WATER BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define I2C_ESTAT_LO_WATER BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define I2C_ESTAT_PORT_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define I2C_ESTAT_SELF_BUSY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I2C_ESTAT_VERSION GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* port busy register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define I2C_PORT_BUSY_RESET BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* wait for command complete or data request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define I2C_CMD_SLEEP_MAX_US 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I2C_CMD_SLEEP_MIN_US 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* wait after reset; choose time from legacy driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define I2C_RESET_SLEEP_MAX_US 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define I2C_RESET_SLEEP_MIN_US 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* choose timeout length from legacy driver; it's well tested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define I2C_ABORT_TIMEOUT msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct fsi_i2c_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct fsi_device *fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct list_head ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct fsi_i2c_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct fsi_i2c_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u16 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int fsi_i2c_read_reg(struct fsi_device *fsi, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) __be32 data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rc = fsi_device_read(fsi, reg, &data_be, sizeof(data_be));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *data = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int fsi_i2c_write_reg(struct fsi_device *fsi, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __be32 data_be = cpu_to_be32p(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return fsi_device_write(fsi, reg, &data_be, sizeof(data_be));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int fsi_i2c_dev_init(struct fsi_i2c_master *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 mode = I2C_MODE_ENHANCED, extended_status, watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 interrupt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* since we use polling, disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mode |= FIELD_PREP(I2C_MODE_CLKDIV, I2C_DEFAULT_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) watermark = FIELD_PREP(I2C_WATERMARK_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i2c->fifo_size - I2C_FIFO_HI_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) watermark |= FIELD_PREP(I2C_WATERMARK_LO, I2C_FIFO_LO_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return fsi_i2c_write_reg(i2c->fsi, I2C_FSI_WATER_MARK, &watermark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int fsi_i2c_set_port(struct fsi_i2c_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct fsi_device *fsi = port->master->fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 mode, dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rc = fsi_i2c_read_reg(fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (FIELD_GET(I2C_MODE_PORT, mode) == port->port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mode = (mode & ~I2C_MODE_PORT) | FIELD_PREP(I2C_MODE_PORT, port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rc = fsi_i2c_write_reg(fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* reset engine when port is changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return fsi_i2c_write_reg(fsi, I2C_FSI_RESET_ERR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int fsi_i2c_start(struct fsi_i2c_port *port, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bool stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 cmd = I2C_CMD_WITH_START | I2C_CMD_WITH_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) port->xfrd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cmd |= I2C_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (stop || msg->flags & I2C_M_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cmd |= I2C_CMD_WITH_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cmd |= FIELD_PREP(I2C_CMD_ADDR, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cmd |= FIELD_PREP(I2C_CMD_LEN, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return fsi_i2c_write_reg(i2c->fsi, I2C_FSI_CMD, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int fsi_i2c_get_op_bytes(int op_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* fsi is limited to max 4 byte aligned ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (op_bytes > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else if (op_bytes == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return op_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int fsi_i2c_write_fifo(struct fsi_i2c_port *port, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 fifo_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int bytes_to_write = i2c->fifo_size - fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int bytes_remaining = msg->len - port->xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bytes_to_write = min(bytes_to_write, bytes_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) while (bytes_to_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) write = fsi_i2c_get_op_bytes(bytes_to_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rc = fsi_device_write(i2c->fsi, I2C_FSI_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) &msg->buf[port->xfrd], write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) port->xfrd += write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bytes_to_write -= write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int fsi_i2c_read_fifo(struct fsi_i2c_port *port, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 fifo_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int bytes_to_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int xfr_remaining = msg->len - port->xfrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bytes_to_read = min_t(int, fifo_count, xfr_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) while (bytes_to_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) read = fsi_i2c_get_op_bytes(bytes_to_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (xfr_remaining) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rc = fsi_device_read(i2c->fsi, I2C_FSI_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) &msg->buf[port->xfrd], read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) port->xfrd += read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) xfr_remaining -= read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* no more buffer but data in fifo, need to clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rc = fsi_device_read(i2c->fsi, I2C_FSI_FIFO, &dummy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bytes_to_read -= read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int fsi_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return !!(stat & I2C_STAT_SCL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void fsi_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SCL, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SCL, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int fsi_i2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return !!(stat & I2C_STAT_SDA_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void fsi_i2c_set_sda(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SDA, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SDA, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void fsi_i2c_prepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mode |= I2C_MODE_DIAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void fsi_i2c_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mode &= ~I2C_MODE_DIAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int fsi_i2c_reset_bus(struct fsi_i2c_master *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct fsi_i2c_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 stat, dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* force bus reset, ignore errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i2c_recover_bus(&port->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* reset errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_ERR, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* wait for command complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) usleep_range(I2C_RESET_SLEEP_MIN_US, I2C_RESET_SLEEP_MAX_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (stat & I2C_STAT_CMD_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* failed to get command complete; reset engine again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* re-init engine again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return fsi_i2c_dev_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int fsi_i2c_reset_engine(struct fsi_i2c_master *i2c, u16 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 mode, dummy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* reset engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* re-init engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rc = fsi_i2c_dev_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* set port; default after reset is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mode &= ~I2C_MODE_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mode |= FIELD_PREP(I2C_MODE_PORT, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* reset busy register; hw workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dummy = I2C_PORT_BUSY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_PORT_BUSY, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int fsi_i2c_abort(struct fsi_i2c_port *port, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 cmd = I2C_CMD_WITH_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct fsi_i2c_master *i2c = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct fsi_device *fsi = i2c->fsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) rc = fsi_i2c_reset_engine(i2c, port->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) rc = fsi_i2c_read_reg(fsi, I2C_FSI_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* if sda is low, peform full bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!(stat & I2C_STAT_SDA_IN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rc = fsi_i2c_reset_bus(i2c, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* skip final stop command for these errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (status & (I2C_STAT_PARITY | I2C_STAT_LOST_ARB | I2C_STAT_STOP_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* write stop command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rc = fsi_i2c_write_reg(fsi, I2C_FSI_CMD, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* wait until we see command complete in the master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rc = fsi_i2c_read_reg(fsi, I2C_FSI_STAT, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (status & I2C_STAT_CMD_COMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) usleep_range(I2C_CMD_SLEEP_MIN_US, I2C_CMD_SLEEP_MAX_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } while (time_after(start + I2C_ABORT_TIMEOUT, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int fsi_i2c_handle_status(struct fsi_i2c_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct i2c_msg *msg, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 fifo_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (status & I2C_STAT_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) rc = fsi_i2c_abort(port, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (status & I2C_STAT_INV_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (status & (I2C_STAT_PARITY | I2C_STAT_BE_OVERRUN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) I2C_STAT_BE_ACCESS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (status & I2C_STAT_NACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (status & I2C_STAT_LOST_ARB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (status & I2C_STAT_STOP_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (status & I2C_STAT_DAT_REQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fifo_count = FIELD_GET(I2C_STAT_FIFO_COUNT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return fsi_i2c_read_fifo(port, msg, fifo_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return fsi_i2c_write_fifo(port, msg, fifo_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (status & I2C_STAT_CMD_COMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (port->xfrd < msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int fsi_i2c_wait(struct fsi_i2c_port *port, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned long start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rc = fsi_i2c_read_reg(port->master->fsi, I2C_FSI_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (status & I2C_STAT_ANY_RESP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rc = fsi_i2c_handle_status(port, msg, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* cmd complete and all data xfrd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (rc == msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* need to xfr more data, but maybe don't need wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) usleep_range(I2C_CMD_SLEEP_MIN_US, I2C_CMD_SLEEP_MAX_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } while (time_after(start + timeout, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned long start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct fsi_i2c_port *port = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct fsi_i2c_master *master = port->master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rc = fsi_i2c_set_port(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) msg = msgs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) rc = fsi_i2c_start(port, msg, i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) rc = fsi_i2c_wait(port, msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) adap->timeout - (jiffies - start_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return rc ? : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static u32 fsi_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return I2C_FUNC_I2C | I2C_FUNC_PROTOCOL_MANGLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct i2c_bus_recovery_info fsi_i2c_bus_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .get_scl = fsi_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .set_scl = fsi_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .get_sda = fsi_i2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .set_sda = fsi_i2c_set_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .prepare_recovery = fsi_i2c_prepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .unprepare_recovery = fsi_i2c_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct i2c_algorithm fsi_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .master_xfer = fsi_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .functionality = fsi_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static struct device_node *fsi_i2c_find_port_of_node(struct device_node *fsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) for_each_child_of_node(fsi, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rc = of_property_read_u32(np, "reg", &port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!rc && port_no == port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int fsi_i2c_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct fsi_i2c_master *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct fsi_i2c_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 port_no, ports, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mutex_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) i2c->fsi = to_fsi_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) INIT_LIST_HEAD(&i2c->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) rc = fsi_i2c_dev_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ports = FIELD_GET(I2C_STAT_MAX_PORT, stat) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_dbg(dev, "I2C master has %d ports\n", ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (port_no = 0; port_no < ports; port_no++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) np = fsi_i2c_find_port_of_node(dev->of_node, port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!of_device_is_available(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) port = kzalloc(sizeof(*port), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) port->master = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) port->port = port_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) port->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) port->adapter.dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) port->adapter.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) port->adapter.algo = &fsi_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) port->adapter.bus_recovery_info = &fsi_i2c_bus_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) port->adapter.algo_data = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) snprintf(port->adapter.name, sizeof(port->adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "i2c_bus-%u", port_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rc = i2c_add_adapter(&port->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(dev, "Failed to register adapter: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) list_add(&port->list, &i2c->ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_set_drvdata(dev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int fsi_i2c_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct fsi_i2c_master *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct fsi_i2c_port *port, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) list_for_each_entry_safe(port, tmp, &i2c->ports, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) list_del(&port->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) i2c_del_adapter(&port->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct fsi_device_id fsi_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { FSI_ENGID_I2C, FSI_VERSION_ANY },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static struct fsi_driver fsi_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .id_table = fsi_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .name = "i2c-fsi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .bus = &fsi_bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .probe = fsi_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .remove = fsi_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) module_fsi_driver(fsi_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) MODULE_AUTHOR("Eddie James <eajames@us.ibm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) MODULE_DESCRIPTION("FSI attached I2C master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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