^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * HSI2C controller from Samsung supports 2 modes of operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 1. Auto mode: Where in master automatically controls the whole transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 2. Manual mode: Software controls the transaction by issuing commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Special bits are available for both modes of operation to set commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * and for checking transfer status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Register Map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HSI2C_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HSI2C_FIFO_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HSI2C_TRAILIG_CTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSI2C_CLK_CTL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HSI2C_CLK_SLOT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HSI2C_INT_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HSI2C_INT_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HSI2C_ERR_STATUS 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HSI2C_FIFO_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HSI2C_TX_DATA 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HSI2C_RX_DATA 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HSI2C_CONF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HSI2C_AUTO_CONF 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HSI2C_TIMEOUT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HSI2C_MANUAL_CMD 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HSI2C_TRANS_STATUS 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HSI2C_TIMING_HS1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HSI2C_TIMING_HS2 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HSI2C_TIMING_HS3 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HSI2C_TIMING_FS1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HSI2C_TIMING_FS2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HSI2C_TIMING_FS3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HSI2C_TIMING_SLA 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HSI2C_ADDR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* I2C_CTL Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HSI2C_FUNC_MODE_I2C (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HSI2C_MASTER (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HSI2C_RXCHON (1u << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HSI2C_TXCHON (1u << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HSI2C_SW_RST (1u << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* I2C_FIFO_CTL Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HSI2C_RXFIFO_EN (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HSI2C_TXFIFO_EN (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* I2C_TRAILING_CTL Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HSI2C_TRAILING_COUNT (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* I2C_INT_EN Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HSI2C_INT_TRAILING_EN (1u << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* I2C_INT_STAT Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HSI2C_INT_TX_UNDERRUN (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HSI2C_INT_TX_OVERRUN (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HSI2C_INT_RX_UNDERRUN (1u << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HSI2C_INT_RX_OVERRUN (1u << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HSI2C_INT_TRAILING (1u << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HSI2C_INT_I2C (1u << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HSI2C_INT_TRANS_DONE (1u << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HSI2C_INT_TRANS_ABORT (1u << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HSI2C_INT_NO_DEV_ACK (1u << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HSI2C_INT_NO_DEV (1u << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HSI2C_INT_TIMEOUT (1u << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) HSI2C_INT_TRANS_ABORT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HSI2C_INT_NO_DEV_ACK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) HSI2C_INT_NO_DEV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) HSI2C_INT_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* I2C_FIFO_STAT Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HSI2C_RX_FIFO_EMPTY (1u << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HSI2C_RX_FIFO_FULL (1u << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HSI2C_TX_FIFO_EMPTY (1u << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HSI2C_TX_FIFO_FULL (1u << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* I2C_CONF Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HSI2C_AUTO_MODE (1u << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HSI2C_10BIT_ADDR_MODE (1u << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HSI2C_HS_MODE (1u << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* I2C_AUTO_CONF Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HSI2C_READ_WRITE (1u << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HSI2C_STOP_AFTER_TRANS (1u << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HSI2C_MASTER_RUN (1u << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* I2C_TIMEOUT Register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HSI2C_TIMEOUT_EN (1u << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HSI2C_TIMEOUT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* I2C_MANUAL_CMD register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HSI2C_CMD_READ_DATA (1u << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HSI2C_CMD_SEND_STOP (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* I2C_TRANS_STATUS register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HSI2C_MASTER_BUSY (1u << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HSI2C_SLAVE_BUSY (1u << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* I2C_TRANS_STATUS register bits for Exynos5 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HSI2C_TIMEOUT_AUTO (1u << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HSI2C_NO_DEV (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HSI2C_NO_DEV_ACK (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HSI2C_TRANS_ABORT (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HSI2C_TRANS_DONE (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* I2C_TRANS_STATUS register bits for Exynos7 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HSI2C_MASTER_ST_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HSI2C_MASTER_ST_IDLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HSI2C_MASTER_ST_START 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HSI2C_MASTER_ST_RESTART 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HSI2C_MASTER_ST_STOP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HSI2C_MASTER_ST_MASTER_ID 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HSI2C_MASTER_ST_ADDR0 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HSI2C_MASTER_ST_ADDR1 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HSI2C_MASTER_ST_ADDR2 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HSI2C_MASTER_ST_ADDR_SR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HSI2C_MASTER_ST_READ 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HSI2C_MASTER_ST_WRITE 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HSI2C_MASTER_ST_NO_ACK 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HSI2C_MASTER_ST_LOSE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HSI2C_MASTER_ST_WAIT 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HSI2C_MASTER_ST_WAIT_CMD 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* I2C_ADDR register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MASTER_ID(x) ((x & 0x7) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum i2c_type_exynos {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) I2C_TYPE_EXYNOS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) I2C_TYPE_EXYNOS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct exynos5_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) spinlock_t lock; /* IRQ synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Since the TRANS_DONE bit is cleared on read, and we may read it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * either during an IRQ or after a transaction, keep track of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * state here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int trans_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Controller operating frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int op_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Version of HS-I2C Hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct exynos_hsi2c_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * struct exynos_hsi2c_variant - platform specific HSI2C driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @fifo_depth: the fifo depth supported by the HSI2C module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @hw: the hardware variant of Exynos I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Specifies platform specific configuration of HSI2C module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Note: A structure for driver specific platform data is used for future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * expansion of its usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct exynos_hsi2c_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enum i2c_type_exynos hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .fifo_depth = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .hw = I2C_TYPE_EXYNOS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .fifo_depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .hw = I2C_TYPE_EXYNOS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .fifo_depth = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .hw = I2C_TYPE_EXYNOS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct of_device_id exynos5_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .compatible = "samsung,exynos5-hsi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .data = &exynos5250_hsi2c_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .compatible = "samsung,exynos5250-hsi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .data = &exynos5250_hsi2c_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .compatible = "samsung,exynos5260-hsi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .data = &exynos5260_hsi2c_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .compatible = "samsung,exynos7-hsi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .data = &exynos7_hsi2c_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }, {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(readl(i2c->regs + HSI2C_INT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) i2c->regs + HSI2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * exynos5_i2c_set_timing: updates the registers with appropriate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * timing values calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Timing values for operation are calculated against either 100kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * or 1MHz controller operating frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Returns 0 on success, -EINVAL if the cycle length cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * be calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 i2c_timing_s1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 i2c_timing_s2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 i2c_timing_s3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 i2c_timing_sla;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int t_start_su, t_start_hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int t_stop_su;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int t_data_su, t_data_hd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int t_scl_l, t_scl_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int t_sr_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int t_ftl_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int clkin = clk_get_rate(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned int op_clk = hs_timings ? i2c->op_clock :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) i2c->op_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int div, clk_cycle, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * In case of HSI2C controller in Exynos5 series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * FPCLK / FI2C =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * In case of HSI2C controllers in Exynos7 series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * FPCLK / FI2C =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * clk_cycle := TSCLK_L + TSCLK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * temp := (CLK_DIV + 1) * (clk_cycle + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) temp = clkin / op_clk - 8 - t_ftl_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) temp -= t_ftl_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) div = temp / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) clk_cycle = temp / (div + 1) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (temp < 4 || div >= 256 || clk_cycle < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(i2c->dev, "%s clock set-up failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) hs_timings ? "HS" : "FS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) t_scl_l = clk_cycle / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) t_scl_h = clk_cycle / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) t_start_su = t_scl_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) t_start_hd = t_scl_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) t_stop_su = t_scl_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) t_data_su = t_scl_l / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) t_data_hd = t_scl_l / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) t_sr_release = clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2c_timing_s3 = div << 16 | t_sr_release << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) i2c_timing_sla = t_data_hd << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) t_start_su, t_start_hd, t_stop_su);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) t_data_su, t_scl_l, t_scl_h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) div, t_sr_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (hs_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* always set Fast Speed timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret = exynos5_i2c_set_timing(i2c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return exynos5_i2c_set_timing(i2c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * exynos5_i2c_init: configures the controller for I2C functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Programs I2C controller for Master mode operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void exynos5_i2c_init(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Clear to disable Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) i2c_timeout &= ~HSI2C_TIMEOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) i2c->regs + HSI2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i2c_conf |= HSI2C_HS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 i2c_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* Set and clear the bit for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) i2c_ctl = readl(i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c_ctl |= HSI2C_SW_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(i2c_ctl, i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) i2c_ctl = readl(i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) i2c_ctl &= ~HSI2C_SW_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(i2c_ctl, i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* We don't expect calculations to fail during the run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) exynos5_hsi2c_clock_setup(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Initialize the configure registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) exynos5_i2c_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * exynos5_i2c_irq: top level IRQ servicing routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * INT_STATUS registers gives the interrupt details. Further,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * state of the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct exynos5_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 fifo_level, int_status, fifo_status, trans_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) i2c->state = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_lock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int_status = readl(i2c->regs + HSI2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) writel(int_status, i2c->regs + HSI2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* handle interrupt related to the transfer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (int_status & HSI2C_INT_TRANS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2c->trans_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else if (int_status & HSI2C_INT_TRANS_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_dbg(i2c->dev, "Deal with arbitration lose\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) i2c->state = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_dbg(i2c->dev, "No ACK from device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) i2c->state = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else if (int_status & HSI2C_INT_NO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_dbg(i2c->dev, "No device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) i2c->state = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else if (int_status & HSI2C_INT_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_dbg(i2c->dev, "Accessing device timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) i2c->state = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) } else if (int_status & HSI2C_INT_I2C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (trans_status & HSI2C_NO_DEV_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_dbg(i2c->dev, "No ACK from device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) i2c->state = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if (trans_status & HSI2C_NO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_dbg(i2c->dev, "No device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) i2c->state = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else if (trans_status & HSI2C_TRANS_ABORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_dbg(i2c->dev, "Deal with arbitration lose\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i2c->state = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(i2c->dev, "Accessing device timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) i2c->state = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else if (trans_status & HSI2C_TRANS_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) i2c->trans_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) i2c->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if ((i2c->msg->flags & I2C_M_RD) && (int_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) byte = (unsigned char)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) readl(i2c->regs + HSI2C_RX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i2c->msg->buf[i2c->msg_ptr++] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) i2c->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) len = i2c->variant->fifo_depth - fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (len > (i2c->msg->len - i2c->msg_ptr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) len = i2c->msg->len - i2c->msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) byte = i2c->msg->buf[i2c->msg_ptr++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel(byte, i2c->regs + HSI2C_TX_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) i2c->state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (i2c->state < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel(0, i2c->regs + HSI2C_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) exynos5_i2c_clr_pend_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) complete(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) spin_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * exynos5_i2c_wait_bus_idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * Returns -EBUSY if the bus cannot be bought to idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long stop_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 trans_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* wait for 100 milli seconds for the bus to be idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) stop_time = jiffies + msecs_to_jiffies(100) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!(trans_status & HSI2C_MASTER_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) usleep_range(50, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } while (time_before(jiffies, stop_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(val, i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(val, i2c->regs + HSI2C_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Specification says master should send nine clock pulses. It can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * emulated by sending manual read command (nine pulses for read eight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * bits + one pulse for NACK).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) exynos5_i2c_wait_bus_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) exynos5_i2c_wait_bus_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) writel(val, i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) writel(val, i2c->regs + HSI2C_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * indicates that bus is stuck (SDA is low). In such case bus recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * can be performed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) timeout = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (time_is_before_jiffies(timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) exynos5_i2c_bus_recover(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * exynos5_i2c_message_start: Configures the bus and starts the xfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * i2c: struct exynos5_i2c pointer for the current bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * stop: Enables stop after transfer if set. Set for last transfer of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * in the list of messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Configures the bus for read/write function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Sets chip address to talk to, message length to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * Enables appropriate interrupts and sends start xfer command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 i2c_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 int_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 i2c_auto_conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 i2c_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 fifo_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned short trig_lvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int_en |= HSI2C_INT_I2C_TRANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int_en |= HSI2C_INT_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) i2c_ctl = readl(i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (i2c->msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) i2c_ctl |= HSI2C_RXCHON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) i2c_auto_conf |= HSI2C_READ_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) HSI2C_INT_TRAILING_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) i2c_ctl |= HSI2C_TXCHON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) writel(i2c_addr, i2c->regs + HSI2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(i2c_ctl, i2c->regs + HSI2C_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) exynos5_i2c_bus_check(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Enable interrupts before starting the transfer so that we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * miss any INT_I2C interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) spin_lock_irqsave(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (stop == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) i2c_auto_conf |= i2c->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) i2c_auto_conf |= HSI2C_MASTER_RUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) spin_unlock_irqrestore(&i2c->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct i2c_msg *msgs, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) i2c->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) i2c->trans_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reinit_completion(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) exynos5_i2c_message_start(i2c, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) timeout = wait_for_completion_timeout(&i2c->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) EXYNOS5_I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = i2c->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * If this is the last message to be transfered (stop == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Then check if the bus can be brought back to idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret == 0 && stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = exynos5_i2c_wait_bus_idle(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) exynos5_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_warn(i2c->dev, "%s timeout\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (msgs->flags & I2C_M_RD) ? "rx" : "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Return the state as in interrupt routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int exynos5_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct exynos5_i2c *i2c = adap->algo_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = 0; i < num; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret ?: num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static u32 exynos5_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const struct i2c_algorithm exynos5_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .master_xfer = exynos5_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .functionality = exynos5_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int exynos5_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct exynos5_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) i2c->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) i2c->adap.algo = &exynos5_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) i2c->adap.retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev_err(&pdev->dev, "cannot get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) i2c->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (IS_ERR(i2c->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ret = PTR_ERR(i2c->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) i2c->adap.dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) i2c->adap.algo_data = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Clear pending interrupts from u-boot or misc causes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) exynos5_i2c_clr_pend_irq(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) spin_lock_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) init_completion(&i2c->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) i2c->irq = ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) i2c->variant = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = exynos5_hsi2c_clock_setup(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) exynos5_i2c_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int exynos5_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int exynos5_i2c_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct exynos5_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) i2c_mark_adapter_suspended(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) clk_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int exynos5_i2c_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct exynos5_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = exynos5_hsi2c_clock_setup(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) exynos5_i2c_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) i2c_mark_adapter_resumed(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) exynos5_i2c_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static struct platform_driver exynos5_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .probe = exynos5_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .remove = exynos5_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .name = "exynos5-hsi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .pm = &exynos5_i2c_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .of_match_table = exynos5_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) module_platform_driver(exynos5_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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