^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * I2C driver for the Renesas EMEV2 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013 Codethink Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2010-2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* I2C Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define I2C_OFS_IICACT0 0x00 /* start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2C_OFS_IIC0 0x04 /* shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_OFS_IICC0 0x08 /* control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_OFS_SVA0 0x0c /* slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_OFS_IICCL0 0x10 /* clock select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_OFS_IICX0 0x14 /* extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_OFS_IICS0 0x18 /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_OFS_IICSE0 0x1c /* status For emulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_OFS_IICF0 0x20 /* IIC flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* I2C IICACT0 Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_BIT_IICE0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* I2C IICC0 Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_BIT_LREL0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_BIT_WREL0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_BIT_SPIE0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_BIT_WTIM0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_BIT_ACKE0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_BIT_STT0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_BIT_SPT0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* I2C IICCL0 Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_BIT_SMC0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_BIT_DFC0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* I2C IICSE0 Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_BIT_MSTS0 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_BIT_ALD0 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_BIT_EXC0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_BIT_COI0 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_BIT_TRC0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_BIT_ACKD0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_BIT_STD0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_BIT_SPD0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* I2C IICF0 Masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_BIT_STCF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_BIT_IICBSY 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_BIT_STCEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_BIT_IICRSV 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct em_i2c_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct completion msg_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct i2c_client *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writeb((readb(priv->base + reg) & ~clear) | set, priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int em_i2c_wait_for_event(struct em_i2c_device *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reinit_completion(&priv->msg_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) time_left = wait_for_completion_timeout(&priv->msg_done, priv->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!time_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) status = readb(priv->base + I2C_OFS_IICSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return status & I2C_BIT_ALD0 ? -EAGAIN : status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void em_i2c_stop(struct em_i2c_device *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Send Stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) em_clear_set_bit(priv, 0, I2C_BIT_SPT0 | I2C_BIT_SPIE0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Wait for stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) em_i2c_wait_for_event(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void em_i2c_reset(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct em_i2c_device *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int retr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* If I2C active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (readb(priv->base + I2C_OFS_IICACT0) & I2C_BIT_IICE0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Disable I2C operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writeb(0, priv->base + I2C_OFS_IICACT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) retr = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while (readb(priv->base + I2C_OFS_IICACT0) == 1 && retr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) retr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) WARN_ON(retr == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Transfer mode set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writeb(I2C_BIT_DFC0, priv->base + I2C_OFS_IICCL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Can Issue start without detecting a stop, Reservation disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writeb(I2C_BIT_STCEN | I2C_BIT_IICRSV, priv->base + I2C_OFS_IICF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* I2C enable, 9 bit interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writeb(I2C_BIT_WTIM0, priv->base + I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Enable I2C operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writeb(I2C_BIT_IICE0, priv->base + I2C_OFS_IICACT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) retr = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) while (readb(priv->base + I2C_OFS_IICACT0) == 0 && retr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) retr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) WARN_ON(retr == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int __em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct em_i2c_device *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int count, status, read = !!(msg->flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Send start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) em_clear_set_bit(priv, 0, I2C_BIT_ACKE0 | I2C_BIT_WTIM0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) em_clear_set_bit(priv, 0, I2C_BIT_STT0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Send slave address and R/W type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writeb(i2c_8bit_addr_from_msg(msg), priv->base + I2C_OFS_IIC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Wait for transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) status = em_i2c_wait_for_event(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto out_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Received NACK (result of setting slave address and R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (!(status & I2C_BIT_ACKD0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) em_i2c_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Extra setup for read transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 8 bit interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Wait for transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) status = em_i2c_wait_for_event(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto out_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Send / receive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (count = 0; count < msg->len; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (read) { /* Read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) msg->buf[count] = readb(priv->base + I2C_OFS_IIC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) em_clear_set_bit(priv, 0, I2C_BIT_WREL0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else { /* Write transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Received NACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!(status & I2C_BIT_ACKD0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) em_i2c_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writeb(msg->buf[count], priv->base + I2C_OFS_IIC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Wait for R/W transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) status = em_i2c_wait_for_event(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto out_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) em_i2c_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) out_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) em_i2c_reset(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return status < 0 ? status : -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int em_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct em_i2c_device *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (readb(priv->base + I2C_OFS_IICF0) & I2C_BIT_IICBSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = __em_i2c_xfer(adap, &msgs[i], (i == (num - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* I2C transfer completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static bool em_i2c_slave_irq(struct em_i2c_device *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 status, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum i2c_slave_event event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!priv->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) status = readb(priv->base + I2C_OFS_IICSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Extension code, do not participate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (status & I2C_BIT_EXC0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Stop detected, we don't know if it's for slave or master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (status & I2C_BIT_SPD0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Notify slave device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Pretend we did not handle the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Only handle interrupts addressed to us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!(status & I2C_BIT_COI0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Enable stop interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) em_clear_set_bit(priv, 0, I2C_BIT_SPIE0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Transmission or Reception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (status & I2C_BIT_TRC0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (status & I2C_BIT_ACKD0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* 9 bit interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) em_clear_set_bit(priv, 0, I2C_BIT_WTIM0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Send data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) event = status & I2C_BIT_STD0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) I2C_SLAVE_READ_REQUESTED :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) I2C_SLAVE_READ_PROCESSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) i2c_slave_event(priv->slave, event, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writeb(value, priv->base + I2C_OFS_IIC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* NACK, stop transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) em_clear_set_bit(priv, 0, I2C_BIT_LREL0, I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* 8 bit interrupt mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_ACKE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) em_clear_set_bit(priv, I2C_BIT_WTIM0, I2C_BIT_WREL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (status & I2C_BIT_STD0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Recv data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) value = readb(priv->base + I2C_OFS_IIC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = i2c_slave_event(priv->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) I2C_SLAVE_WRITE_RECEIVED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) em_clear_set_bit(priv, I2C_BIT_ACKE0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) I2C_OFS_IICC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static irqreturn_t em_i2c_irq_handler(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct em_i2c_device *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (em_i2c_slave_irq(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) complete(&priv->msg_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u32 em_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int em_i2c_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (priv->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) priv->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writeb(slave->addr << 1, priv->base + I2C_OFS_SVA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int em_i2c_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct em_i2c_device *priv = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) WARN_ON(!priv->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writeb(0, priv->base + I2C_OFS_SVA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Wait for interrupt to finish. New slave irqs cannot happen because we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * cleared the slave address and, thus, only extension codes will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * detected which do not use the slave ptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) synchronize_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) priv->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct i2c_algorithm em_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .master_xfer = em_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .functionality = em_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .reg_slave = em_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .unreg_slave = em_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int em_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct em_i2c_device *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) strlcpy(priv->adap.name, "EMEV2 I2C", sizeof(priv->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->sclk = devm_clk_get(&pdev->dev, "sclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(priv->sclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return PTR_ERR(priv->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = clk_prepare_enable(priv->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) priv->adap.timeout = msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) priv->adap.retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) priv->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) priv->adap.algo = &em_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) priv->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) priv->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) init_completion(&priv->msg_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) em_i2c_reset(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) priv->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "em_i2c", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = i2c_add_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk_disable_unprepare(priv->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int em_i2c_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct em_i2c_device *priv = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) clk_disable_unprepare(priv->sclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct of_device_id em_i2c_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { .compatible = "renesas,iic-emev2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct platform_driver em_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .probe = em_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .remove = em_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .name = "em-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .of_match_table = em_i2c_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_platform_driver(em_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DESCRIPTION("EMEV2 I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_AUTHOR("Ian Molton");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_DEVICE_TABLE(of, em_i2c_ids);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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