Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DRIVER_NAME "efm32-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MASK_VAL(mask, val)		((val << __ffs(mask)) & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define REG_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_CTRL_EN			0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_CTRL_SLAVE			0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_CTRL_AUTOACK		0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CTRL_AUTOSE			0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_CTRL_AUTOSN			0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_CTRL_ARBDIS			0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_CTRL_GCAMEN			0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_CTRL_CLHR__MASK		0x00300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_CTRL_BITO__MASK		0x03000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_CTRL_BITO_OFF		0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_CTRL_BITO_40PCC		0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_CTRL_BITO_80PCC		0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_CTRL_BITO_160PCC		0x03000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_CTRL_GIBITO			0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_CTRL_CLTO__MASK		0x70000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_CTRL_CLTO_OFF		0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_CMD			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_CMD_START			0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_CMD_STOP			0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_CMD_ACK			0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_CMD_NACK			0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_CMD_CONT			0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_CMD_ABORT			0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_CMD_CLEARTX			0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_CMD_CLEARPC			0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_STATE		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define REG_STATE_BUSY			0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG_STATE_MASTER		0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_STATE_TRANSMITTER		0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_STATE_NACKED		0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG_STATE_BUSHOLD		0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define REG_STATE_STATE__MASK		0x000e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG_STATE_STATE_IDLE		0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define REG_STATE_STATE_WAIT		0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define REG_STATE_STATE_START		0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG_STATE_STATE_ADDR		0x00060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_STATE_STATE_ADDRACK		0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define REG_STATE_STATE_DATA		0x000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_STATE_STATE_DATAACK		0x000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_STATUS		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REG_STATUS_PSTART		0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define REG_STATUS_PSTOP		0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_STATUS_PACK			0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_STATUS_PNACK		0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_STATUS_PCONT		0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_STATUS_PABORT		0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_STATUS_TXC			0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REG_STATUS_TXBL			0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define REG_STATUS_RXDATAV		0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define REG_CLKDIV		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define REG_CLKDIV_DIV__MASK		0x001ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define REG_CLKDIV_DIV(div)		MASK_VAL(REG_CLKDIV_DIV__MASK, (div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define REG_SADDR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define REG_SADDRMASK		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define REG_RXDATA		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define REG_RXDATAP		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define REG_TXDATA		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define REG_IF			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define REG_IF_START			0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define REG_IF_RSTART			0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define REG_IF_ADDR			0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define REG_IF_TXC			0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define REG_IF_TXBL			0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define REG_IF_RXDATAV			0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define REG_IF_ACK			0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define REG_IF_NACK			0x00080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define REG_IF_MSTOP			0x00100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define REG_IF_ARBLOST			0x00200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define REG_IF_BUSERR			0x00400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define REG_IF_BUSHOLD			0x00800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define REG_IF_TXOF			0x01000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define REG_IF_RXUF			0x02000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define REG_IF_BITO			0x04000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define REG_IF_CLTO			0x08000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define REG_IF_SSTOP			0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define REG_IFS			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_IFC			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_IFC__MASK			0x1ffcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_IEN			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_ROUTE		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_ROUTE_SDAPEN		0x00001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_ROUTE_SCLPEN		0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_ROUTE_LOCATION__MASK	0x00700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_ROUTE_LOCATION(n)		MASK_VAL(REG_ROUTE_LOCATION__MASK, (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct efm32_i2c_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned long frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* transfer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct completion done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct i2c_msg *msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	size_t num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	size_t current_word, current_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return readl(ddata->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		unsigned offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	writel(value, ddata->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	efm32_i2c_write32(ddata, REG_TXDATA, i2c_8bit_addr_from_msg(cur_msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (ddata->current_word >= cur_msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* cur_msg completely transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		ddata->current_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		ddata->current_msg += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		if (ddata->current_msg >= ddata->num_msgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			efm32_i2c_send_next_msg(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		efm32_i2c_write32(ddata, REG_TXDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				cur_msg->buf[ddata->current_word++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ddata->current_word += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (ddata->current_word >= cur_msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		/* cur_msg completely transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		ddata->current_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		ddata->current_msg += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (ddata->current_msg >= ddata->num_msgs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			efm32_i2c_send_next_msg(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static irqreturn_t efm32_i2c_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct efm32_i2c_ddata *ddata = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 irqflag = efm32_i2c_read32(ddata, REG_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 state = efm32_i2c_read32(ddata, REG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	switch (state & REG_STATE_STATE__MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case REG_STATE_STATE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		/* arbitration lost? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		ddata->retval = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case REG_STATE_STATE_WAIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		 * huh, this shouldn't happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		 * Reset hardware state and get out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		ddata->retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		efm32_i2c_write32(ddata, REG_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				REG_CMD_STOP | REG_CMD_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				REG_CMD_CLEARTX | REG_CMD_CLEARPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	case REG_STATE_STATE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		/* "caller" is expected to send an address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	case REG_STATE_STATE_ADDR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		/* wait for Ack or NAck of slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case REG_STATE_STATE_ADDRACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (state & REG_STATE_NACKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			ddata->retval = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		} else if (cur_msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			/* wait for slave to send first data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			efm32_i2c_send_next_byte(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case REG_STATE_STATE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (cur_msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			efm32_i2c_recv_next_byte(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			/* wait for Ack or Nack of slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	case REG_STATE_STATE_DATAACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		if (state & REG_STATE_NACKED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			complete(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			efm32_i2c_send_next_byte(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int efm32_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ddata->msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ddata->msgs = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ddata->num_msgs = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ddata->current_word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ddata->current_msg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ddata->retval = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	reinit_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			efm32_i2c_read32(ddata, REG_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			efm32_i2c_read32(ddata, REG_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	efm32_i2c_send_next_msg(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	wait_for_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (ddata->current_msg >= ddata->num_msgs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		ret = ddata->num_msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = ddata->retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static u32 efm32_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct i2c_algorithm efm32_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.master_xfer = efm32_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.functionality = efm32_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u32 reg = efm32_i2c_read32(ddata, REG_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return (reg & REG_ROUTE_LOCATION__MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		__ffs(REG_ROUTE_LOCATION__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int efm32_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct efm32_i2c_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u32 location, frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u32 clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	platform_set_drvdata(pdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	init_completion(&ddata->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	ddata->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ddata->adapter.algo = &efm32_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ddata->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	ddata->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	i2c_set_adapdata(&ddata->adapter, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	ddata->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (IS_ERR(ddata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		ret = PTR_ERR(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (IS_ERR(ddata->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		return PTR_ERR(ddata->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (resource_size(res) < 0x42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_err(&pdev->dev, "memory resource too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ddata->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	ret = clk_prepare_enable(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	ret = of_property_read_u32(np, "energymicro,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		/* fall back to wrongly namespaced property */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		ret = of_property_read_u32(np, "efm32,location", &location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_dbg(&pdev->dev, "using location %u\n", location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		/* default to location configured in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		location = efm32_i2c_get_configured_location(ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_info(&pdev->dev, "fall back to location %u\n", location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	ddata->location = location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	ret = of_property_read_u32(np, "clock-frequency", &frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		dev_dbg(&pdev->dev, "using frequency %u\n", frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		frequency = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dev_info(&pdev->dev, "defaulting to 100 kHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	ddata->frequency = frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	rate = clk_get_rate(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (!rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		dev_err(&pdev->dev, "there is no input clock available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (clkdiv >= 0x200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 				"input clock too fast (%lu) to divide down to bus freq (%lu)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 				rate, ddata->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			rate, ddata->frequency, (unsigned long)clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			REG_ROUTE_SCLPEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			REG_ROUTE_LOCATION(ddata->location));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			| REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	/* to make bus idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		dev_err(&pdev->dev, "failed to request irq (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	ret = i2c_add_adapter(&ddata->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		free_irq(ddata->irq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int efm32_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	i2c_del_adapter(&ddata->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	free_irq(ddata->irq, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	clk_disable_unprepare(ddata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const struct of_device_id efm32_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		.compatible = "energymicro,efm32-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		/* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct platform_driver efm32_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.probe = efm32_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.remove = efm32_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.of_match_table = efm32_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) module_platform_driver(efm32_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_DESCRIPTION("EFM32 i2c driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_ALIAS("platform:" DRIVER_NAME);