Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Synopsys DesignWare I2C adapter driver (slave only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on the Synopsys DesignWare I2C adapter driver (master).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2016 Synopsys Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "i2c-designware-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	/* Configure Tx/Rx FIFO threshold levels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	regmap_write(dev->map, DW_IC_TX_TL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	regmap_write(dev->map, DW_IC_RX_TL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/* Configure the I2C slave. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	regmap_write(dev->map, DW_IC_CON, dev->slave_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * i2c_dw_init_slave() - Initialize the designware i2c slave hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @dev: device private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * This function configures and enables the I2C in slave mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * This function is called during I2C init function, and in case of timeout at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * run time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	ret = i2c_dw_acquire_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	/* Disable the adapter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	__i2c_dw_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* Write SDA hold time if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (dev->sda_hold_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	i2c_dw_configure_fifo_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	i2c_dw_release_lock(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int i2c_dw_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	if (dev->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	if (slave->flags & I2C_CLIENT_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return -EAFNOSUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	pm_runtime_get_sync(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * Set slave address in the IC_SAR register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * the address to which the DW_apb_i2c responds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__i2c_dw_disable_nowait(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	regmap_write(dev->map, DW_IC_SAR, slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	dev->slave = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__i2c_dw_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dev->cmd_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	dev->msg_write_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dev->msg_read_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	dev->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	dev->status = STATUS_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	dev->abort_source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	dev->rx_outstanding = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static int i2c_dw_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	dev->disable_int(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dev->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	synchronize_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	dev->slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	pm_runtime_put(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 stat, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * The IC_INTR_STAT register just indicates "enabled" interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * The unmasked raw version of interrupt status bits is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * in the IC_RAW_INTR_STAT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 * That is,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 *   stat = readl(IC_INTR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * equals to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 *   stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * The raw version might be useful for debugging purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * Do not use the IC_CLR_INTR register to clear interrupts, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * you'll miss some interrupts, triggered during the period from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * Instead, use the separately-prepared IC_CLR_* registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (stat & DW_IC_INTR_TX_ABRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (stat & DW_IC_INTR_RX_UNDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (stat & DW_IC_INTR_RX_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (stat & DW_IC_INTR_TX_OVER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (stat & DW_IC_INTR_RX_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (stat & DW_IC_INTR_ACTIVITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (stat & DW_IC_INTR_STOP_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (stat & DW_IC_INTR_START_DET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (stat & DW_IC_INTR_GEN_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * Interrupt service routine. This gets called whenever an I2C slave interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 raw_stat, stat, enabled, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u8 val = 0, slave_activity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	regmap_read(dev->map, DW_IC_ENABLE, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	regmap_read(dev->map, DW_IC_STATUS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	slave_activity = ((tmp & DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	stat = i2c_dw_read_clear_intrbits_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	dev_dbg(dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		"%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		enabled, slave_activity, raw_stat, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (stat & DW_IC_INTR_RX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		if (dev->status != STATUS_WRITE_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			dev->status = STATUS_WRITE_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					&val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		val = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				     &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			dev_vdbg(dev->dev, "Byte %X acked!", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (stat & DW_IC_INTR_RD_REQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (slave_activity) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			regmap_read(dev->map, DW_IC_CLR_RD_REQ, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			dev->status = STATUS_READ_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			if (!i2c_slave_event(dev->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 					     I2C_SLAVE_READ_REQUESTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 					     &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				regmap_write(dev->map, DW_IC_DATA_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (stat & DW_IC_INTR_RX_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				     &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			regmap_read(dev->map, DW_IC_CLR_RX_DONE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (stat & DW_IC_INTR_STOP_DET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		dev->status = STATUS_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct dw_i2c_dev *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ret = i2c_dw_irq_handler_slave(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return IRQ_RETVAL(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct i2c_algorithm i2c_dw_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.functionality = i2c_dw_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.reg_slave = i2c_dw_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.unreg_slave = i2c_dw_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void i2c_dw_configure_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dev->functionality = I2C_FUNC_SLAVE | DW_IC_DEFAULT_FUNCTIONALITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	dev->slave_cfg = DW_IC_CON_RX_FIFO_FULL_HLD_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			 DW_IC_CON_RESTART_EN | DW_IC_CON_STOP_DET_IFADDRESSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	dev->mode = DW_IC_SLAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXPORT_SYMBOL_GPL(i2c_dw_configure_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct i2c_adapter *adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	dev->init = i2c_dw_init_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	dev->disable = i2c_dw_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	dev->disable_int = i2c_dw_disable_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = i2c_dw_init_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	ret = i2c_dw_set_sda_hold(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ret = i2c_dw_set_fifo_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret = dev->init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	snprintf(adap->name, sizeof(adap->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		 "Synopsys DesignWare I2C Slave adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	adap->algo = &i2c_dw_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	adap->dev.parent = dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			       IRQF_SHARED, dev_name(dev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(dev->dev, "failure requesting irq %i: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			dev->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_err(dev->dev, "failure adding adapter: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EXPORT_SYMBOL_GPL(i2c_dw_probe_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_LICENSE("GPL v2");