Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Synopsys DesignWare I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on the TI DAVINCI I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2007 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2009 Provigent Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/platform_data/i2c-designware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "i2c-designware-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return clk_get_rate(dev->clk)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const struct acpi_device_id dw_i2c_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ "INT33C2", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ "INT33C3", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ "INT3432", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ "INT3433", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ "80860F41", ACCESS_NO_IRQ_SUSPEND },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ "808622C1", ACCESS_NO_IRQ_SUSPEND },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{ "AMD0010", ACCESS_INTR_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	{ "AMDI0010", ACCESS_INTR_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{ "AMDI0510", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{ "APMC0D0F", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{ "HISI02A1", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ "HISI02A2", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ "HISI02A3", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ "HYGO0010", ACCESS_INTR_MASK },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define BT1_I2C_CTL			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define BT1_I2C_CTL_ADDR_MASK		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define BT1_I2C_CTL_WR			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define BT1_I2C_CTL_GO			BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BT1_I2C_DI			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BT1_I2C_DO			0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * Note these methods shouldn't ever fail because the system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * registers are memory mapped. We check the return value just in case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ret = regmap_write(dev->sysmap, BT1_I2C_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			   BT1_I2C_CTL_GO | (reg & BT1_I2C_CTL_ADDR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return regmap_read(dev->sysmap, BT1_I2C_DO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct dw_i2c_dev *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	ret = regmap_write(dev->sysmap, BT1_I2C_DI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return regmap_write(dev->sysmap, BT1_I2C_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		BT1_I2C_CTL_GO | BT1_I2C_CTL_WR | (reg & BT1_I2C_CTL_ADDR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct regmap_config bt1_i2c_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.reg_read = bt1_i2c_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.reg_write = bt1_i2c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.max_register = DW_IC_COMP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (IS_ERR(dev->sysmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		return PTR_ERR(dev->sysmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	dev->map = devm_regmap_init(dev->dev, NULL, dev, &bt1_i2c_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return PTR_ERR_OR_ZERO(dev->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MSCC_ICPU_CFG_TWI_DELAY		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MSCC_ICPU_CFG_TWI_SPIKE_FILTER	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	       dev->ext + MSCC_ICPU_CFG_TWI_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int dw_i2c_of_configure(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	switch (dev->flags & MODEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	case MODEL_MSCC_OCELOT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		dev->ext = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (!IS_ERR(dev->ext))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct of_device_id dw_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ .compatible = "snps,designware-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ .compatible = "baikal,bt1-sys-i2c", .data = (void *)MODEL_BAIKAL_BT1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline int dw_i2c_of_configure(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	pm_runtime_disable(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (dev->shared_with_punit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		pm_runtime_put_noidle(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct platform_device *pdev = to_platform_device(dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (dev->flags & MODEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case MODEL_BAIKAL_BT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = bt1_i2c_request_regs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		dev->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = PTR_ERR_OR_ZERO(dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct dmi_system_id dw_i2c_hwmon_class_dmi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.ident = "Qtechnology QT5222",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			DMI_MATCH(DMI_SYS_VENDOR, "Qtechnology"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			DMI_MATCH(DMI_PRODUCT_NAME, "QT5222"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int dw_i2c_plat_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct dw_i2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct dw_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct i2c_timings *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dev->flags = (uintptr_t)device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = dw_i2c_plat_request_regs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	dev->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (IS_ERR(dev->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return PTR_ERR(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	reset_control_deassert(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	t = &dev->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		t->bus_freq_hz = pdata->i2c_scl_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		i2c_parse_fw_timings(&pdev->dev, t, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	i2c_dw_adjust_bus_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		dw_i2c_of_configure(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (has_acpi_companion(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		i2c_dw_acpi_configure(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	ret = i2c_dw_validate_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		goto exit_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	ret = i2c_dw_probe_lock_support(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		goto exit_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	i2c_dw_configure(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Optional interface clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (IS_ERR(dev->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		ret = PTR_ERR(dev->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		goto exit_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!i2c_dw_prepare_clk(dev, true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		u64 clk_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		clk_khz = dev->get_clk_rate_khz(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (!dev->sda_hold_time && t->sda_hold_ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			dev->sda_hold_time =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				div_u64(clk_khz * t->sda_hold_ns + 500000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	adap->class = dmi_check_system(dw_i2c_hwmon_class_dmi) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 					I2C_CLASS_HWMON : I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	adap->nr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dev_pm_set_driver_flags(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					DPM_FLAG_SMART_PREPARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 					DPM_FLAG_MAY_SKIP_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		dev_pm_set_driver_flags(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					DPM_FLAG_SMART_PREPARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 					DPM_FLAG_SMART_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 					DPM_FLAG_MAY_SKIP_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* The code below assumes runtime PM to be disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	WARN_ON(pm_runtime_enabled(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (dev->shared_with_punit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	ret = i2c_dw_probe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		goto exit_probe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) exit_probe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	dw_i2c_plat_pm_cleanup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) exit_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	reset_control_assert(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int dw_i2c_plat_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	dev->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	dw_i2c_plat_pm_cleanup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	reset_control_assert(dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int dw_i2c_plat_prepare(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 * If the ACPI companion device object is present for this device, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	 * may be accessed during suspend and resume of other devices via I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	 * operation regions, so tell the PM core and middle layers to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	 * skipping system suspend/resume callbacks for it in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return !has_acpi_companion(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void dw_i2c_plat_complete(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	 * The device can only be in runtime suspend at this point if it has not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 * been resumed throughout the ending system suspend/resume cycle, so if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 * the platform firmware might mess up with it, request the runtime PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 * framework to resume it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (pm_runtime_suspended(dev) && pm_resume_via_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		pm_request_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define dw_i2c_plat_prepare	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define dw_i2c_plat_complete	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int dw_i2c_plat_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	i_dev->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (i_dev->shared_with_punit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	i_dev->disable(i_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	i2c_dw_prepare_clk(i_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int dw_i2c_plat_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (!i_dev->shared_with_punit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		i2c_dw_prepare_clk(i_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	i_dev->init(i_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	i_dev->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct dev_pm_ops dw_i2c_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.prepare = dw_i2c_plat_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.complete = dw_i2c_plat_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	SET_RUNTIME_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DW_I2C_DEV_PMOPS (&dw_i2c_dev_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DW_I2C_DEV_PMOPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_ALIAS("platform:i2c_designware");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct platform_driver dw_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.probe = dw_i2c_plat_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.remove = dw_i2c_plat_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		.name	= "i2c_designware",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		.of_match_table = of_match_ptr(dw_i2c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		.acpi_match_table = ACPI_PTR(dw_i2c_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		.pm	= DW_I2C_DEV_PMOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int __init dw_i2c_init_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	return platform_driver_register(&dw_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) subsys_initcall(dw_i2c_init_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void __exit dw_i2c_exit_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	platform_driver_unregister(&dw_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) module_exit(dw_i2c_exit_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_LICENSE("GPL");