Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Synopsys DesignWare I2C adapter driver (master only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on the TI DAVINCI I2C adapter driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2007 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2009 Provigent Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 2011, 2015, 2016 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "i2c-designware-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRIVER_NAME "i2c-designware-pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum dw_pci_ctl_id_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	medfield,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	merrifield,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	baytrail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	cherrytrail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	haswell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	elkhartlake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct dw_scl_sda_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u16 ss_hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u16 fs_hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u16 ss_lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u16 fs_lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 sda_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct dw_pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct dw_scl_sda_cfg *scl_sda_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32 (*get_clk_rate_khz)(struct dw_i2c_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Merrifield HCNT/LCNT/SDA hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static struct dw_scl_sda_cfg mrfld_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.ss_hcnt = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.fs_hcnt = 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.ss_lcnt = 0x37b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.fs_lcnt = 0x10a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* BayTrail HCNT/LCNT/SDA hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct dw_scl_sda_cfg byt_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.ss_hcnt = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.fs_hcnt = 0x55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.ss_lcnt = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.fs_lcnt = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.sda_hold = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Haswell HCNT/LCNT/SDA hold time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct dw_scl_sda_cfg hsw_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.ss_hcnt = 0x01b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.fs_hcnt = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.ss_lcnt = 0x01fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.fs_lcnt = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.sda_hold = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	case 0x0817:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case 0x0818:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case 0x0819:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		c->bus_num = pdev->device - 0x817 + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case 0x082C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case 0x082D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case 0x082E:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		c->bus_num = pdev->device - 0x82C + 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * On Intel Merrifield the user visible i2c buses are enumerated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * [1..7]. So, we add 1 to shift the default range. Besides that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 * first PCI slot provides 4 functions, that's why we have to add 0 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	 * the first slot and 4 to the next one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	switch (PCI_SLOT(pdev->devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		c->bus_num = PCI_FUNC(pdev->devfn) + 0 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		c->bus_num = PCI_FUNC(pdev->devfn) + 4 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u32 ehl_get_clk_rate_khz(struct dw_i2c_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct dw_pci_controller dw_pci_controllers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[medfield] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.setup = mfld_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.get_clk_rate_khz = mfld_get_clk_rate_khz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	[merrifield] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.scl_sda_cfg = &mrfld_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.setup = mrfld_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	[baytrail] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.scl_sda_cfg = &byt_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	[haswell] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.scl_sda_cfg = &hsw_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	[cherrytrail] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.scl_sda_cfg = &byt_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	[elkhartlake] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.bus_num = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.get_clk_rate_khz = ehl_get_clk_rate_khz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int i2c_dw_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	i_dev->suspended = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	i_dev->disable(i_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int i2c_dw_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret = i_dev->init(i_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	i_dev->suspended = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			    i2c_dw_pci_resume, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int i2c_dw_pci_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			    const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct dw_i2c_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct dw_pci_controller *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct dw_scl_sda_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	controller = &dw_pci_controllers[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	r = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(&pdev->dev, "I/O memory remapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	r = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	dev->get_clk_rate_khz = controller->get_clk_rate_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	dev->timings.bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	dev->base = pcim_iomap_table(pdev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	dev->irq = pci_irq_vector(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	dev->flags |= controller->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (controller->setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		r = controller->setup(pdev, controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	i2c_dw_adjust_bus_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (has_acpi_companion(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		i2c_dw_acpi_configure(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	r = i2c_dw_validate_speed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	i2c_dw_configure(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (controller->scl_sda_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		cfg = controller->scl_sda_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		dev->ss_hcnt = cfg->ss_hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		dev->fs_hcnt = cfg->fs_hcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		dev->ss_lcnt = cfg->ss_lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		dev->fs_lcnt = cfg->fs_lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev->sda_hold_time = cfg->sda_hold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	adap->class = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	adap->nr = controller->bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	r = i2c_dw_probe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void i2c_dw_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dev->disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	pm_runtime_forbid(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	devm_free_irq(&pdev->dev, dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_ALIAS("i2c_designware-pci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct pci_device_id i2_designware_pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Medfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ PCI_VDEVICE(INTEL, 0x0817), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ PCI_VDEVICE(INTEL, 0x0818), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ PCI_VDEVICE(INTEL, 0x0819), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ PCI_VDEVICE(INTEL, 0x082C), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ PCI_VDEVICE(INTEL, 0x082D), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ PCI_VDEVICE(INTEL, 0x082E), medfield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* Merrifield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ PCI_VDEVICE(INTEL, 0x1195), merrifield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ PCI_VDEVICE(INTEL, 0x1196), merrifield },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* Baytrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ PCI_VDEVICE(INTEL, 0x0F43), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	{ PCI_VDEVICE(INTEL, 0x0F44), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	{ PCI_VDEVICE(INTEL, 0x0F45), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ PCI_VDEVICE(INTEL, 0x0F46), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	{ PCI_VDEVICE(INTEL, 0x0F47), baytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* Haswell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{ PCI_VDEVICE(INTEL, 0x9c61), haswell },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ PCI_VDEVICE(INTEL, 0x9c62), haswell },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* Braswell / Cherrytrail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ PCI_VDEVICE(INTEL, 0x22C1), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	{ PCI_VDEVICE(INTEL, 0x22C2), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	{ PCI_VDEVICE(INTEL, 0x22C3), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ PCI_VDEVICE(INTEL, 0x22C4), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ PCI_VDEVICE(INTEL, 0x22C5), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{ PCI_VDEVICE(INTEL, 0x22C6), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ PCI_VDEVICE(INTEL, 0x22C7), cherrytrail },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* Elkhart Lake (PSE I2C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ PCI_VDEVICE(INTEL, 0x4bb9), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ PCI_VDEVICE(INTEL, 0x4bba), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ PCI_VDEVICE(INTEL, 0x4bbb), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ PCI_VDEVICE(INTEL, 0x4bbc), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ PCI_VDEVICE(INTEL, 0x4bbd), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{ PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{ 0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct pci_driver dw_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.name		= DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.id_table	= i2_designware_pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.probe		= i2c_dw_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.remove		= i2c_dw_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.driver         = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.pm     = &i2c_dw_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) module_pci_driver(dw_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_LICENSE("GPL");